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authorTom Musta <tommusta@gmail.com>2013-09-25 17:42:46 +1000
committerAlexander Graf <agraf@suse.de>2013-10-25 23:25:45 +0200
commitbbfb6f132abc032229f5c1f25e6e959861c6f759 (patch)
treeb7a4fdb8428be4ae74620c06ac7ebd88f1ac0360 /target-ppc/mem_helper.c
parent04f1f7842e18c4b5e50203cc5b207cafb7c62974 (diff)
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target-ppc: Little Endian Correction to Load/Store Vector Element
The Load Vector Element (lve*x) and Store Vector Element (stve*x) instructions not only byte-swap in Little Endian mode, they also invert the element that is accessed. For example, the RTL for lvehx contains this: eb <-- EA[60:63] if Big-Endian byte ordering then VRT[8*eb:8*eb+15] <-- MEM(EA,2) else VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2) This patch adds the element inversion, as described in the last line of the RTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mem_helper.c')
-rw-r--r--target-ppc/mem_helper.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index d8e63ca..f35ed03 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -212,6 +212,7 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
int index = (addr & 0xf) >> sh; \
\
if (msr_le) { \
+ index = n_elems - index - 1; \
r->element[LO_IDX ? index : (adjust - index)] = \
swap(access(env, addr)); \
} else { \
@@ -236,6 +237,7 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32)
int index = (addr & 0xf) >> sh; \
\
if (msr_le) { \
+ index = n_elems - index - 1; \
access(env, addr, swap(r->element[LO_IDX ? index : \
(adjust - index)])); \
} else { \