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| author | Tom Musta <tommusta@gmail.com> | 2014-03-31 16:03:58 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-04-08 11:20:02 +0200 |
| commit | d359db00e6dfaf12cbdedd30e36f879110d4f9d1 (patch) | |
| tree | f1b4d414461d61fada01daacc59d2a29783af873 /target-ppc/fpu_helper.c | |
| parent | 80189035de73f30e42a7f933c45cccfc4b0c56e9 (diff) | |
| download | qemu-d359db00e6dfaf12cbdedd30e36f879110d4f9d1.zip qemu-d359db00e6dfaf12cbdedd30e36f879110d4f9d1.tar.gz qemu-d359db00e6dfaf12cbdedd30e36f879110d4f9d1.tar.bz2 | |
target-ppc: Correct LE Host Inversion of Lower VSRs
This change properly orders the doublewords of the VSRs 0-31. Because these
registers are constructed from separate doublewords, they must be inverted
on Little Endian hosts. The inversion is performed both when the VSR is read
and when it is written.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/fpu_helper.c')
| -rw-r--r-- | target-ppc/fpu_helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index d79aae9..9fc7dd8 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1793,8 +1793,8 @@ typedef union _ppc_vsr_t { static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - vsr->f64[0] = env->fpr[n]; - vsr->u64[1] = env->vsr[n]; + vsr->VsrD(0) = env->fpr[n]; + vsr->VsrD(1) = env->vsr[n]; } else { vsr->u64[0] = env->avr[n-32].u64[0]; vsr->u64[1] = env->avr[n-32].u64[1]; @@ -1804,8 +1804,8 @@ static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - env->fpr[n] = vsr->f64[0]; - env->vsr[n] = vsr->u64[1]; + env->fpr[n] = vsr->VsrD(0); + env->vsr[n] = vsr->VsrD(1); } else { env->avr[n-32].u64[0] = vsr->u64[0]; env->avr[n-32].u64[1] = vsr->u64[1]; |