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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-27 19:30:47 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-27 19:30:47 +0000 |
| commit | 6a6ae23f3c7c80e66e8e900ed9820c7134997a36 (patch) | |
| tree | 1a7419541c2e1c9712d6d6f125867b44ac298d1e /target-ppc/exec.h | |
| parent | 38d14952014790c8c7f5c098f8048be594a4385d (diff) | |
| download | qemu-6a6ae23f3c7c80e66e8e900ed9820c7134997a36.zip qemu-6a6ae23f3c7c80e66e8e900ed9820c7134997a36.tar.gz qemu-6a6ae23f3c7c80e66e8e900ed9820c7134997a36.tar.bz2 | |
target-ppc: convert SPE load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/exec.h')
| -rw-r--r-- | target-ppc/exec.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 4541383..a86e052 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -44,16 +44,6 @@ register target_ulong T1 asm(AREG2); register target_ulong T2 asm(AREG3); #define TDX "%016lx" #endif -/* We may, sometime, need 64 bits registers on 32 bits targets */ -#if !defined(TARGET_PPC64) -#define T0_64 (env->t0_64) -#define T1_64 (env->t1_64) -#define T2_64 (env->t2_64) -#else -#define T0_64 T0 -#define T1_64 T1 -#define T2_64 T2 -#endif #define FT0 (env->ft0) #define FT1 (env->ft1) |