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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-06-21 23:48:52 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-06-23 12:43:54 +1000 |
| commit | b781537560e3b968b6fe1395e3d07bd67f0009ba (patch) | |
| tree | 6ebdcbaedc66c5c6964d461cfecf8cd83efb89e6 /target-ppc/cpu.h | |
| parent | 9b2fadda3e0196ffd485adde4fe9cdd6fae35300 (diff) | |
| download | qemu-b781537560e3b968b6fe1395e3d07bd67f0009ba.zip qemu-b781537560e3b968b6fe1395e3d07bd67f0009ba.tar.gz qemu-b781537560e3b968b6fe1395e3d07bd67f0009ba.tar.bz2 | |
ppc: Add real mode CI load/store instructions for P7 and P8
Those instructions are only available in hypervisor real mode and
allow cache inhibited garded access to devices in that mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index f005549..61a24b1 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1912,6 +1912,8 @@ enum { PPC_POPCNTB = 0x0000000000001000ULL, /* string load / store */ PPC_STRING = 0x0000000000002000ULL, + /* real mode cache inhibited load / store */ + PPC_CILDST = 0x0000000000004000ULL, /* Floating-point unit extensions */ /* Optional floating point instructions */ @@ -2026,7 +2028,7 @@ enum { | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ - | PPC_POPCNTWD) + | PPC_POPCNTWD | PPC_CILDST) /* extended type values */ |