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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:51:05 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:45 +0200 |
| commit | d5ac4f543352c3412172fb72256137defb13a4b1 (patch) | |
| tree | 3152964851f905c3fb93ff30889657ba03e74b4f /target-ppc/cpu.h | |
| parent | c4015bbd502d670d88e5689e1143e36ea097c76f (diff) | |
| download | qemu-d5ac4f543352c3412172fb72256137defb13a4b1.zip qemu-d5ac4f543352c3412172fb72256137defb13a4b1.tar.gz qemu-d5ac4f543352c3412172fb72256137defb13a4b1.tar.bz2 | |
spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for TCG.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 32ee652..74407ee 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -467,6 +467,8 @@ struct ppc_slb_t { #define MSR_LE 0 /* Little-endian mode 1 hflags */ #define LPCR_ILE (1 << (63-38)) +#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */ +#define LPCR_AIL (3 << LPCR_AIL_SHIFT) #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) @@ -2010,7 +2012,7 @@ enum { PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ - PPC2_ALTIVEC_207) + PPC2_ALTIVEC_207 | PPC2_ISA207S) }; /*****************************************************************************/ |