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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:59 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:45 +0200 |
| commit | cdcdda27fc843873875e7e444e0164ba2a5e9942 (patch) | |
| tree | 7b490295f1b369fbe608407ab00e0c5c166d5b88 /target-ppc/cpu.h | |
| parent | 70c5340744f044d2195216d0e3c7c0c554dbd7ca (diff) | |
| download | qemu-cdcdda27fc843873875e7e444e0164ba2a5e9942.zip qemu-cdcdda27fc843873875e7e444e0164ba2a5e9942.tar.gz qemu-cdcdda27fc843873875e7e444e0164ba2a5e9942.tar.bz2 | |
target-ppc: Add POWER8's TM SPRs
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the helpers.
This adds a gen_msr_facility_check() helper which purpose is to generate
the Facility Unavailable exception if the facility is disabled.
It is a copy of gen_fscr_facility_check() but it checks for enabled
facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
in FSCR/HFSCR (whichever is passed to the helper).
This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
which are used for TM SPRs.
This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
msr_mask.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d19e284..a85916e 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -427,6 +427,9 @@ struct ppc_slb_t { #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ #define MSR_SHV 60 /* hypervisor state hflags */ +#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ +#define MSR_TS1 33 +#define MSR_TM 32 /* Transactional Memory Available (Book3s) */ #define MSR_CM 31 /* Computation mode for BookE hflags */ #define MSR_ICM 30 /* Interrupt computation mode for BookE */ #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ @@ -503,6 +506,9 @@ struct ppc_slb_t { #define msr_pmm ((env->msr >> MSR_PMM) & 1) #define msr_ri ((env->msr >> MSR_RI) & 1) #define msr_le ((env->msr >> MSR_LE) & 1) +#define msr_ts ((env->msr >> MSR_TS1) & 3) +#define msr_tm ((env->msr >> MSR_TM) & 1) + /* Hypervisor bit is more specific */ #if defined(TARGET_PPC64) #define MSR_HVB (1ULL << MSR_SHV) @@ -1271,6 +1277,10 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_EIE (0x050) #define SPR_MPC_EID (0x051) #define SPR_MPC_NRI (0x052) +#define SPR_TFHAR (0x080) +#define SPR_TFIAR (0x081) +#define SPR_TEXASR (0x082) +#define SPR_TEXASRU (0x083) #define SPR_UCTRL (0x088) #define SPR_MPC_CMPA (0x090) #define SPR_MPC_CMPB (0x091) |