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| author | Tom Musta <tommusta@gmail.com> | 2014-12-18 10:34:33 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:27 +0100 |
| commit | aac862379ceaa724aba2ba9f4b825479c1401b1a (patch) | |
| tree | 15cf9d46148e8431c9f9d0856e905805e43a4d24 /target-ppc/cpu.h | |
| parent | 3e28c5e363aaf3de8b99acb662b7488ed6b49197 (diff) | |
| download | qemu-aac862379ceaa724aba2ba9f4b825479c1401b1a.zip qemu-aac862379ceaa724aba2ba9f4b825479c1401b1a.tar.gz qemu-aac862379ceaa724aba2ba9f4b825479c1401b1a.tar.bz2 | |
target-ppc: Introduce TEXASRU Bit Fields
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 38176c0..91a03f6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -558,6 +558,26 @@ struct ppc_slb_t { #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ +/* Transaction EXception And Summary Register bits */ +#define TEXASR_FAILURE_PERSISTENT (63 - 7) +#define TEXASR_DISALLOWED (63 - 8) +#define TEXASR_NESTING_OVERFLOW (63 - 9) +#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) +#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) +#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) +#define TEXASR_TRANSACTION_CONFLICT (63 - 13) +#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) +#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) +#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) +#define TEXASR_ABORT (63 - 31) +#define TEXASR_SUSPENDED (63 - 32) +#define TEXASR_PRIVILEGE_HV (63 - 34) +#define TEXASR_PRIVILEGE_PR (63 - 35) +#define TEXASR_FAILURE_SUMMARY (63 - 36) +#define TEXASR_TFIAR_EXACT (63 - 37) +#define TEXASR_ROT (63 - 38) +#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ + enum { POWERPC_FLAG_NONE = 0x00000000, /* Flag for MSR bit 25 signification (VRE/SPE) */ |