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| author | Thomas Huth <thuth@linux.vnet.ibm.com> | 2012-02-27 17:18:08 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-03-15 13:12:11 +0100 |
| commit | cd6e9320142fea0d9e82c8ca7f3a4c2f20fecf39 (patch) | |
| tree | 6d081d141f1d5edf48678112a50d8cdb93d55801 /target-ppc/cpu.h | |
| parent | b5aec39672dc6084b43fa3f77764a6f549255a53 (diff) | |
| download | qemu-cd6e9320142fea0d9e82c8ca7f3a4c2f20fecf39.zip qemu-cd6e9320142fea0d9e82c8ca7f3a4c2f20fecf39.tar.gz qemu-cd6e9320142fea0d9e82c8ca7f3a4c2f20fecf39.tar.bz2 | |
PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index ad09cbe..ca6f1cb 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1918,8 +1918,10 @@ enum { PPC2_DFP = 0x0000000000000004ULL, /* Embedded.Processor Control */ PPC2_PRCNTL = 0x0000000000000008ULL, + /* Byte-reversed, indexed, double-word load and store */ + PPC2_DBRX = 0x0000000000000010ULL, -#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL) +#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX) }; /*****************************************************************************/ |