diff options
author | Alexander Graf <agraf@suse.de> | 2011-06-17 01:00:28 +0200 |
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committer | Alexander Graf <agraf@suse.de> | 2011-06-17 02:58:37 +0200 |
commit | 1c53accceeb01246aea0ec361e1efd15cac6db0f (patch) | |
tree | 19d6bae7c21f0d852d5a1af0ad63b61a3d84fabf /target-ppc/cpu.h | |
parent | 0dd4bc7dd45de7afa88662d24bd50a3aafdbab64 (diff) | |
download | qemu-1c53accceeb01246aea0ec361e1efd15cac6db0f.zip qemu-1c53accceeb01246aea0ec361e1efd15cac6db0f.tar.gz qemu-1c53accceeb01246aea0ec361e1efd15cac6db0f.tar.bz2 |
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types and
allocated that union. While it's a waste of memory (and cache) to allocate
TLB information for a TLB type with much information when you only need
little, it also inflicts another issue.
With the new KVM API, we can now share the TLB between KVM and qemu, but
for that to work we need to have both be in the same layout. We can't just
stretch it over to fit some internal different TLB representation.
Hence this patch moves all TLB types to their own array, allowing us to only
address and allocate exactly the boundaries required for the specific TLB
type at hand.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r-- | target-ppc/cpu.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 758c554..46d86be 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -368,10 +368,16 @@ typedef struct ppcmas_tlb_t { } ppcmas_tlb_t; union ppc_tlb_t { - ppc6xx_tlb_t tlb6; - ppcemb_tlb_t tlbe; - ppcmas_tlb_t tlbm; + ppc6xx_tlb_t *tlb6; + ppcemb_tlb_t *tlbe; + ppcmas_tlb_t *tlbm; }; + +/* possible TLB variants */ +#define TLB_NONE 0 +#define TLB_6XX 1 +#define TLB_EMB 2 +#define TLB_MAS 3 #endif #define SDR_32_HTABORG 0xFFFF0000UL @@ -911,7 +917,8 @@ struct CPUPPCState { int last_way; /* Last used way used to allocate TLB in a LRU way */ int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ int nb_pids; /* Number of available PID registers */ - ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ + int tlb_type; /* Type of TLB we're dealing with */ + ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ /* 403 dedicated access protection registers */ target_ulong pb[4]; #endif @@ -1942,9 +1949,9 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls) static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm) { uintptr_t tlbml = (uintptr_t)tlbm; - uintptr_t tlbl = (uintptr_t)env->tlb; + uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; - return (tlbml - tlbl) / sizeof(env->tlb[0]); + return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); } static inline int booke206_tlb_size(CPUState *env, int tlbn) @@ -2004,7 +2011,7 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn, r += booke206_tlb_size(env, i); } - return &env->tlb[r].tlbm; + return &env->tlb.tlbm[r]; } #endif |