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| author | Alexander Graf <agraf@suse.de> | 2012-06-20 21:27:02 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:52 +0200 |
| commit | 2a7a47fc6c19703a849a34243701a09052cb1bc6 (patch) | |
| tree | b7206463004047ffd2d1349c0c4c4ea7831d3f7c /target-ppc/cpu.h | |
| parent | e42a61f185f859246c14445b6e98e195eb3b977b (diff) | |
| download | qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.zip qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.tar.gz qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.tar.bz2 | |
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7a77fff..652a35a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1066,6 +1066,7 @@ struct CPUPPCState { target_ulong ivor_mask; target_ulong ivpr_mask; target_ulong hreset_vector; + target_phys_addr_t mpic_cpu_base; #endif /* Those resources are used only during code translation */ |