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| author | Richard Henderson <rth@twiddle.net> | 2012-09-18 21:55:34 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-09-19 21:40:47 +0200 |
| commit | fb7729e2d03e1ffb4306f2411c18aa20f737dba8 (patch) | |
| tree | b257effe2eb1ccf867ae56f4a93b79998e8d827e /target-mips | |
| parent | 9fa7748873c99cbf8b281650bdc18fd442be4743 (diff) | |
| download | qemu-fb7729e2d03e1ffb4306f2411c18aa20f737dba8.zip qemu-fb7729e2d03e1ffb4306f2411c18aa20f737dba8.tar.gz qemu-fb7729e2d03e1ffb4306f2411c18aa20f737dba8.tar.bz2 | |
target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debugging
enabled from creeping back in.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 31 |
1 files changed, 17 insertions, 14 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index f93b444..4e04e97 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -28,7 +28,7 @@ #define GEN_HELPER 1 #include "helper.h" -//#define MIPS_DEBUG_DISAS +#define MIPS_DEBUG_DISAS 0 //#define MIPS_DEBUG_SIGN_EXTENSIONS /* MIPS major opcodes */ @@ -566,22 +566,25 @@ static const char *fregnames[] = "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; -#ifdef MIPS_DEBUG_DISAS -#define MIPS_DEBUG(fmt, ...) \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x " fmt "\n", \ - ctx->pc, ctx->opcode , ## __VA_ARGS__) -#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -#define MIPS_DEBUG(fmt, ...) do { } while(0) -#define LOG_DISAS(...) do { } while (0) -#endif +#define MIPS_DEBUG(fmt, ...) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x " fmt "\n", \ + ctx->pc, ctx->opcode , ## __VA_ARGS__); \ + } \ + } while (0) + +#define LOG_DISAS(...) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ + } \ + } while (0) #define MIPS_INVAL(op) \ -do { \ MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ -} while (0) + ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)) /* General purpose registers moves. */ static inline void gen_load_gpr (TCGv t, int reg) |