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authorMaciej W. Rozycki <macro@codesourcery.com>2014-12-02 22:31:33 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2014-12-16 12:45:20 +0000
commit66991d1103562591eba6b801049720976317fe61 (patch)
tree7045479681aa21ccca45215d5307ebf61ff5fc20 /target-mips
parent1a4d570017bf35d99340781ecb59dd3772464031 (diff)
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target-mips: Fix DisasContext's ulri member initialization
Set DisasContext's ulri member to 0 or 1 as with other bool members. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 571b7d7..f65ed84 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19116,7 +19116,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
- ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
+ ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;