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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-17 14:43:54 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-17 14:43:54 +0000
commita7812ae412311d7d47f8aa85656faadac9d64b56 (patch)
treebae5e0d6fe19739e5e6d1cdc75d84312bf175257 /target-mips
parent30913bae9a2cf92b5a87363ec1c7d0ad1f82cdcc (diff)
downloadqemu-a7812ae412311d7d47f8aa85656faadac9d64b56.zip
qemu-a7812ae412311d7d47f8aa85656faadac9d64b56.tar.gz
qemu-a7812ae412311d7d47f8aa85656faadac9d64b56.tar.bz2
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/helper.h400
-rw-r--r--target-mips/op_helper.c21
-rw-r--r--target-mips/translate.c2016
3 files changed, 1212 insertions, 1225 deletions
diff --git a/target-mips/helper.h b/target-mips/helper.h
index f67c82a..cc36bb1 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -1,215 +1,218 @@
-#ifndef DEF_HELPER
-#define DEF_HELPER(ret, name, params) ret name params;
-#endif
+#include "def-helper.h"
+
+/* FIXME: We should rename the helper functions and remove this hack. */
+#undef HELPER
+#define HELPER(name) do_##name
-DEF_HELPER(void, do_raise_exception_err, (int excp, int err))
-DEF_HELPER(void, do_raise_exception, (int excp))
-DEF_HELPER(void, do_interrupt_restart, (void))
+
+DEF_HELPER_2(raise_exception_err, void, i32, int)
+DEF_HELPER_1(raise_exception, void, i32)
+DEF_HELPER_0(interrupt_restart, void)
#ifdef TARGET_MIPS64
-DEF_HELPER(target_ulong, do_ldl, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(target_ulong, do_ldr, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(void, do_sdl, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(void, do_sdr, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER_3(ldl, tl, tl, tl, int)
+DEF_HELPER_3(ldr, tl, tl, tl, int)
+DEF_HELPER_3(sdl, void, tl, tl, int)
+DEF_HELPER_3(sdr, void, tl, tl, int)
#endif
-DEF_HELPER(target_ulong, do_lwl, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(target_ulong, do_lwr, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(void, do_swl, (target_ulong t0, target_ulong t1, int mem_idx))
-DEF_HELPER(void, do_swr, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER_3(lwl, tl, tl, tl, int)
+DEF_HELPER_3(lwr, tl, tl, tl, int)
+DEF_HELPER_3(swl, void, tl, tl, int)
+DEF_HELPER_3(swr, void, tl, tl, int)
-DEF_HELPER(target_ulong, do_clo, (target_ulong t0))
-DEF_HELPER(target_ulong, do_clz, (target_ulong t0))
+DEF_HELPER_1(clo, tl, tl)
+DEF_HELPER_1(clz, tl, tl)
#ifdef TARGET_MIPS64
-DEF_HELPER(target_ulong, do_dclo, (target_ulong t0))
-DEF_HELPER(target_ulong, do_dclz, (target_ulong t0))
-DEF_HELPER(void, do_dmult, (target_ulong t0, target_ulong t1))
-DEF_HELPER(void, do_dmultu, (target_ulong t0, target_ulong t1))
+DEF_HELPER_1(dclo, tl, tl)
+DEF_HELPER_1(dclz, tl, tl)
+DEF_HELPER_2(dmult, void, tl, tl)
+DEF_HELPER_2(dmultu, void, tl, tl)
#endif
-DEF_HELPER(target_ulong, do_muls, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_mulsu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_macc, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_maccu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_msac, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_msacu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_mulhi, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_mulhiu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_mulshi, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_mulshiu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_macchi, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
+DEF_HELPER_2(muls, tl, tl, tl)
+DEF_HELPER_2(mulsu, tl, tl, tl)
+DEF_HELPER_2(macc, tl, tl, tl)
+DEF_HELPER_2(maccu, tl, tl, tl)
+DEF_HELPER_2(msac, tl, tl, tl)
+DEF_HELPER_2(msacu, tl, tl, tl)
+DEF_HELPER_2(mulhi, tl, tl, tl)
+DEF_HELPER_2(mulhiu, tl, tl, tl)
+DEF_HELPER_2(mulshi, tl, tl, tl)
+DEF_HELPER_2(mulshiu, tl, tl, tl)
+DEF_HELPER_2(macchi, tl, tl, tl)
+DEF_HELPER_2(macchiu, tl, tl, tl)
+DEF_HELPER_2(msachi, tl, tl, tl)
+DEF_HELPER_2(msachiu, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
-DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
-DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
-DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
-DEF_HELPER(target_ulong, do_mfc0_random, (void))
-DEF_HELPER(target_ulong, do_mfc0_tcstatus, (void))
-DEF_HELPER(target_ulong, do_mftc0_tcstatus, (void))
-DEF_HELPER(target_ulong, do_mfc0_tcbind, (void))
-DEF_HELPER(target_ulong, do_mftc0_tcbind, (void))
-DEF_HELPER(target_ulong, do_mfc0_tcrestart, (void))
-DEF_HELPER(target_ulong, do_mftc0_tcrestart, (void))
-DEF_HELPER(target_ulong, do_mfc0_tchalt, (void))
-DEF_HELPER(target_ulong, do_mftc0_tchalt, (void))
-DEF_HELPER(target_ulong, do_mfc0_tccontext, (void))
-DEF_HELPER(target_ulong, do_mftc0_tccontext, (void))
-DEF_HELPER(target_ulong, do_mfc0_tcschedule, (void))
-DEF_HELPER(target_ulong, do_mftc0_tcschedule, (void))
-DEF_HELPER(target_ulong, do_mfc0_tcschefback, (void))
-DEF_HELPER(target_ulong, do_mftc0_tcschefback, (void))
-DEF_HELPER(target_ulong, do_mfc0_count, (void))
-DEF_HELPER(target_ulong, do_mftc0_entryhi, (void))
-DEF_HELPER(target_ulong, do_mftc0_status, (void))
-DEF_HELPER(target_ulong, do_mfc0_lladdr, (void))
-DEF_HELPER(target_ulong, do_mfc0_watchlo, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mfc0_watchhi, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mfc0_debug, (void))
-DEF_HELPER(target_ulong, do_mftc0_debug, (void))
+DEF_HELPER_0(mfc0_mvpcontrol, tl)
+DEF_HELPER_0(mfc0_mvpconf0, tl)
+DEF_HELPER_0(mfc0_mvpconf1, tl)
+DEF_HELPER_0(mfc0_random, tl)
+DEF_HELPER_0(mfc0_tcstatus, tl)
+DEF_HELPER_0(mftc0_tcstatus, tl)
+DEF_HELPER_0(mfc0_tcbind, tl)
+DEF_HELPER_0(mftc0_tcbind, tl)
+DEF_HELPER_0(mfc0_tcrestart, tl)
+DEF_HELPER_0(mftc0_tcrestart, tl)
+DEF_HELPER_0(mfc0_tchalt, tl)
+DEF_HELPER_0(mftc0_tchalt, tl)
+DEF_HELPER_0(mfc0_tccontext, tl)
+DEF_HELPER_0(mftc0_tccontext, tl)
+DEF_HELPER_0(mfc0_tcschedule, tl)
+DEF_HELPER_0(mftc0_tcschedule, tl)
+DEF_HELPER_0(mfc0_tcschefback, tl)
+DEF_HELPER_0(mftc0_tcschefback, tl)
+DEF_HELPER_0(mfc0_count, tl)
+DEF_HELPER_0(mftc0_entryhi, tl)
+DEF_HELPER_0(mftc0_status, tl)
+DEF_HELPER_0(mfc0_lladdr, tl)
+DEF_HELPER_1(mfc0_watchlo, tl, i32)
+DEF_HELPER_1(mfc0_watchhi, tl, i32)
+DEF_HELPER_0(mfc0_debug, tl)
+DEF_HELPER_0(mftc0_debug, tl)
#ifdef TARGET_MIPS64
-DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (void))
-DEF_HELPER(target_ulong, do_dmfc0_tchalt, (void))
-DEF_HELPER(target_ulong, do_dmfc0_tccontext, (void))
-DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (void))
-DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (void))
-DEF_HELPER(target_ulong, do_dmfc0_lladdr, (void))
-DEF_HELPER(target_ulong, do_dmfc0_watchlo, (uint32_t sel))
+DEF_HELPER_0(dmfc0_tcrestart, tl)
+DEF_HELPER_0(dmfc0_tchalt, tl)
+DEF_HELPER_0(dmfc0_tccontext, tl)
+DEF_HELPER_0(dmfc0_tcschedule, tl)
+DEF_HELPER_0(dmfc0_tcschefback, tl)
+DEF_HELPER_0(dmfc0_lladdr, tl)
+DEF_HELPER_1(dmfc0_watchlo, tl, i32)
#endif /* TARGET_MIPS64 */
-DEF_HELPER(void, do_mtc0_index, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_mvpcontrol, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_vpecontrol, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_vpeconf0, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_vpeconf1, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_yqmask, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_vpeopt, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_entrylo0, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tcstatus, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tcstatus, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tcbind, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tcbind, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tcrestart, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tcrestart, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tchalt, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tchalt, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tccontext, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tccontext, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tcschedule, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tcschedule, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_tcschefback, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_tcschefback, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_entrylo1, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_context, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_pagemask, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_pagegrain, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_wired, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsconf0, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsconf1, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsconf2, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsconf3, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsconf4, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_hwrena, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_count, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_entryhi, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_entryhi, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_compare, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_status, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_status, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_intctl, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_srsctl, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_cause, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_ebase, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_config0, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_config2, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_watchlo, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mtc0_watchhi, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mtc0_xcontext, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_framemask, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_debug, (target_ulong t0))
-DEF_HELPER(void, do_mttc0_debug, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_performance0, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
-DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
+DEF_HELPER_1(mtc0_index, void, tl)
+DEF_HELPER_1(mtc0_mvpcontrol, void, tl)
+DEF_HELPER_1(mtc0_vpecontrol, void, tl)
+DEF_HELPER_1(mtc0_vpeconf0, void, tl)
+DEF_HELPER_1(mtc0_vpeconf1, void, tl)
+DEF_HELPER_1(mtc0_yqmask, void, tl)
+DEF_HELPER_1(mtc0_vpeopt, void, tl)
+DEF_HELPER_1(mtc0_entrylo0, void, tl)
+DEF_HELPER_1(mtc0_tcstatus, void, tl)
+DEF_HELPER_1(mttc0_tcstatus, void, tl)
+DEF_HELPER_1(mtc0_tcbind, void, tl)
+DEF_HELPER_1(mttc0_tcbind, void, tl)
+DEF_HELPER_1(mtc0_tcrestart, void, tl)
+DEF_HELPER_1(mttc0_tcrestart, void, tl)
+DEF_HELPER_1(mtc0_tchalt, void, tl)
+DEF_HELPER_1(mttc0_tchalt, void, tl)
+DEF_HELPER_1(mtc0_tccontext, void, tl)
+DEF_HELPER_1(mttc0_tccontext, void, tl)
+DEF_HELPER_1(mtc0_tcschedule, void, tl)
+DEF_HELPER_1(mttc0_tcschedule, void, tl)
+DEF_HELPER_1(mtc0_tcschefback, void, tl)
+DEF_HELPER_1(mttc0_tcschefback, void, tl)
+DEF_HELPER_1(mtc0_entrylo1, void, tl)
+DEF_HELPER_1(mtc0_context, void, tl)
+DEF_HELPER_1(mtc0_pagemask, void, tl)
+DEF_HELPER_1(mtc0_pagegrain, void, tl)
+DEF_HELPER_1(mtc0_wired, void, tl)
+DEF_HELPER_1(mtc0_srsconf0, void, tl)
+DEF_HELPER_1(mtc0_srsconf1, void, tl)
+DEF_HELPER_1(mtc0_srsconf2, void, tl)
+DEF_HELPER_1(mtc0_srsconf3, void, tl)
+DEF_HELPER_1(mtc0_srsconf4, void, tl)
+DEF_HELPER_1(mtc0_hwrena, void, tl)
+DEF_HELPER_1(mtc0_count, void, tl)
+DEF_HELPER_1(mtc0_entryhi, void, tl)
+DEF_HELPER_1(mttc0_entryhi, void, tl)
+DEF_HELPER_1(mtc0_compare, void, tl)
+DEF_HELPER_1(mtc0_status, void, tl)
+DEF_HELPER_1(mttc0_status, void, tl)
+DEF_HELPER_1(mtc0_intctl, void, tl)
+DEF_HELPER_1(mtc0_srsctl, void, tl)
+DEF_HELPER_1(mtc0_cause, void, tl)
+DEF_HELPER_1(mtc0_ebase, void, tl)
+DEF_HELPER_1(mtc0_config0, void, tl)
+DEF_HELPER_1(mtc0_config2, void, tl)
+DEF_HELPER_2(mtc0_watchlo, void, tl, i32)
+DEF_HELPER_2(mtc0_watchhi, void, tl, i32)
+DEF_HELPER_1(mtc0_xcontext, void, tl)
+DEF_HELPER_1(mtc0_framemask, void, tl)
+DEF_HELPER_1(mtc0_debug, void, tl)
+DEF_HELPER_1(mttc0_debug, void, tl)
+DEF_HELPER_1(mtc0_performance0, void, tl)
+DEF_HELPER_1(mtc0_taglo, void, tl)
+DEF_HELPER_1(mtc0_datalo, void, tl)
+DEF_HELPER_1(mtc0_taghi, void, tl)
+DEF_HELPER_1(mtc0_datahi, void, tl)
/* MIPS MT functions */
-DEF_HELPER(target_ulong, do_mftgpr, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mftlo, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mfthi, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mftacx, (uint32_t sel))
-DEF_HELPER(target_ulong, do_mftdsp, (void))
-DEF_HELPER(void, do_mttgpr, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mttlo, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mtthi, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mttacx, (target_ulong t0, uint32_t sel))
-DEF_HELPER(void, do_mttdsp, (target_ulong t0))
-DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
-DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
-DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
-DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
+DEF_HELPER_1(mftgpr, tl, i32);
+DEF_HELPER_1(mftlo, tl, i32)
+DEF_HELPER_1(mfthi, tl, i32)
+DEF_HELPER_1(mftacx, tl, i32)
+DEF_HELPER_0(mftdsp, tl)
+DEF_HELPER_2(mttgpr, void, tl, i32)
+DEF_HELPER_2(mttlo, void, tl, i32)
+DEF_HELPER_2(mtthi, void, tl, i32)
+DEF_HELPER_2(mttacx, void, tl, i32)
+DEF_HELPER_1(mttdsp, void, tl)
+DEF_HELPER_1(dmt, tl, tl)
+DEF_HELPER_1(emt, tl, tl)
+DEF_HELPER_1(dvpe, tl, tl)
+DEF_HELPER_1(evpe, tl, tl)
#endif /* !CONFIG_USER_ONLY */
-DEF_HELPER(void, do_fork, (target_ulong t0, target_ulong t1))
-DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
+DEF_HELPER_2(fork, void, tl, tl)
+DEF_HELPER_1(yield, tl, tl)
/* CP1 functions */
-DEF_HELPER(target_ulong, do_cfc1, (uint32_t reg))
-DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg))
+DEF_HELPER_1(cfc1, tl, i32)
+DEF_HELPER_2(ctc1, void, tl, i32)
-DEF_HELPER(uint64_t, do_float_cvtd_s, (uint32_t fst0))
-DEF_HELPER(uint64_t, do_float_cvtd_w, (uint32_t wt0))
-DEF_HELPER(uint64_t, do_float_cvtd_l, (uint64_t dt0))
-DEF_HELPER(uint64_t, do_float_cvtl_d, (uint64_t fd0))
-DEF_HELPER(uint64_t, do_float_cvtl_s, (uint32_t fst0))
-DEF_HELPER(uint64_t, do_float_cvtps_pw, (uint64_t dt0))
-DEF_HELPER(uint64_t, do_float_cvtpw_ps, (uint64_t fdt0))
-DEF_HELPER(uint32_t, do_float_cvts_d, (uint64_t fd0))
-DEF_HELPER(uint32_t, do_float_cvts_w, (uint32_t wt0))
-DEF_HELPER(uint32_t, do_float_cvts_l, (uint64_t dt0))
-DEF_HELPER(uint32_t, do_float_cvts_pl, (uint32_t wt0))
-DEF_HELPER(uint32_t, do_float_cvts_pu, (uint32_t wth0))
-DEF_HELPER(uint32_t, do_float_cvtw_s, (uint32_t fst0))
-DEF_HELPER(uint32_t, do_float_cvtw_d, (uint64_t fd0))
+DEF_HELPER_1(float_cvtd_s, i64, i32)
+DEF_HELPER_1(float_cvtd_w, i64, i32)
+DEF_HELPER_1(float_cvtd_l, i64, i64)
+DEF_HELPER_1(float_cvtl_d, i64, i64)
+DEF_HELPER_1(float_cvtl_s, i64, i32)
+DEF_HELPER_1(float_cvtps_pw, i64, i64)
+DEF_HELPER_1(float_cvtpw_ps, i64, i64)
+DEF_HELPER_1(float_cvts_d, i32, i64)
+DEF_HELPER_1(float_cvts_w, i32, i32)
+DEF_HELPER_1(float_cvts_l, i32, i64)
+DEF_HELPER_1(float_cvts_pl, i32, i32)
+DEF_HELPER_1(float_cvts_pu, i32, i32)
+DEF_HELPER_1(float_cvtw_s, i32, i32)
+DEF_HELPER_1(float_cvtw_d, i32, i64)
-DEF_HELPER(uint64_t, do_float_addr_ps, (uint64_t fdt0, uint64_t fdt1))
-DEF_HELPER(uint64_t, do_float_mulr_ps, (uint64_t fdt0, uint64_t fdt1))
+DEF_HELPER_2(float_addr_ps, i64, i64, i64)
+DEF_HELPER_2(float_mulr_ps, i64, i64, i64)
-#define FOP_PROTO(op) \
-DEF_HELPER(uint64_t, do_float_ ## op ## l_s, (uint32_t fst0)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## l_d, (uint64_t fdt0)) \
-DEF_HELPER(uint32_t, do_float_ ## op ## w_s, (uint32_t fst0)) \
-DEF_HELPER(uint32_t, do_float_ ## op ## w_d, (uint64_t fdt0))
+#define FOP_PROTO(op) \
+DEF_HELPER_1(float_ ## op ## l_s, i64, i32) \
+DEF_HELPER_1(float_ ## op ## l_d, i64, i64) \
+DEF_HELPER_1(float_ ## op ## w_s, i32, i32) \
+DEF_HELPER_1(float_ ## op ## w_d, i32, i64)
FOP_PROTO(round)
FOP_PROTO(trunc)
FOP_PROTO(ceil)
FOP_PROTO(floor)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0))
+#define FOP_PROTO(op) \
+DEF_HELPER_1(float_ ## op ## _s, i32, i32) \
+DEF_HELPER_1(float_ ## op ## _d, i64, i64)
FOP_PROTO(sqrt)
FOP_PROTO(rsqrt)
FOP_PROTO(recip)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0))
+#define FOP_PROTO(op) \
+DEF_HELPER_1(float_ ## op ## _s, i32, i32) \
+DEF_HELPER_1(float_ ## op ## _d, i64, i64) \
+DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
FOP_PROTO(abs)
FOP_PROTO(chs)
FOP_PROTO(recip1)
FOP_PROTO(rsqrt1)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0, uint32_t fst2)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0, uint64_t fdt2)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0, uint64_t fdt2))
+#define FOP_PROTO(op) \
+DEF_HELPER_2(float_ ## op ## _s, i32, i32, i32) \
+DEF_HELPER_2(float_ ## op ## _d, i64, i64, i64) \
+DEF_HELPER_2(float_ ## op ## _ps, i64, i64, i64)
FOP_PROTO(add)
FOP_PROTO(sub)
FOP_PROTO(mul)
@@ -218,26 +221,23 @@ FOP_PROTO(recip2)
FOP_PROTO(rsqrt2)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER(uint32_t, do_float_ ## op ## _s, (uint32_t fst0, uint32_t fst1, \
- uint32_t fst2)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _d, (uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2)) \
-DEF_HELPER(uint64_t, do_float_ ## op ## _ps, (uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2))
+#define FOP_PROTO(op) \
+DEF_HELPER_3(float_ ## op ## _s, i32, i32, i32, i32) \
+DEF_HELPER_3(float_ ## op ## _d, i64, i64, i64, i64) \
+DEF_HELPER_3(float_ ## op ## _ps, i64, i64, i64, i64)
FOP_PROTO(muladd)
FOP_PROTO(mulsub)
FOP_PROTO(nmuladd)
FOP_PROTO(nmulsub)
#undef FOP_PROTO
-#define FOP_PROTO(op) \
-DEF_HELPER(void, do_cmp_d_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
-DEF_HELPER(void, do_cmpabs_d_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
-DEF_HELPER(void, do_cmp_s_ ## op, (uint32_t fst0, uint32_t fst1, int cc)) \
-DEF_HELPER(void, do_cmpabs_s_ ## op, (uint32_t fst0, uint32_t fst1, int cc)) \
-DEF_HELPER(void, do_cmp_ps_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc)) \
-DEF_HELPER(void, do_cmpabs_ps_ ## op, (uint64_t fdt0, uint64_t fdt1, int cc))
+#define FOP_PROTO(op) \
+DEF_HELPER_3(cmp_d_ ## op, void, i64, i64, int) \
+DEF_HELPER_3(cmpabs_d_ ## op, void, i64, i64, int) \
+DEF_HELPER_3(cmp_s_ ## op, void, i32, i32, int) \
+DEF_HELPER_3(cmpabs_s_ ## op, void, i32, i32, int) \
+DEF_HELPER_3(cmp_ps_ ## op, void, i64, i64, int) \
+DEF_HELPER_3(cmpabs_ps_ ## op, void, i64, i64, int)
FOP_PROTO(f)
FOP_PROTO(un)
FOP_PROTO(eq)
@@ -258,14 +258,20 @@ FOP_PROTO(ngt)
/* Special functions */
#ifndef CONFIG_USER_ONLY
-DEF_HELPER(target_ulong, do_di, (void))
-DEF_HELPER(target_ulong, do_ei, (void))
-DEF_HELPER(void, do_eret, (void))
-DEF_HELPER(void, do_deret, (void))
+DEF_HELPER_0(tlbwi, void)
+DEF_HELPER_0(tlbwr, void)
+DEF_HELPER_0(tlbp, void)
+DEF_HELPER_0(tlbr, void)
+DEF_HELPER_0(di, tl)
+DEF_HELPER_0(ei, tl)
+DEF_HELPER_0(eret, void)
+DEF_HELPER_0(deret, void)
#endif /* !CONFIG_USER_ONLY */
-DEF_HELPER(target_ulong, do_rdhwr_cpunum, (void))
-DEF_HELPER(target_ulong, do_rdhwr_synci_step, (void))
-DEF_HELPER(target_ulong, do_rdhwr_cc, (void))
-DEF_HELPER(target_ulong, do_rdhwr_ccres, (void))
-DEF_HELPER(void, do_pmon, (int function))
-DEF_HELPER(void, do_wait, (void))
+DEF_HELPER_0(rdhwr_cpunum, tl)
+DEF_HELPER_0(rdhwr_synci_step, tl)
+DEF_HELPER_0(rdhwr_cc, tl)
+DEF_HELPER_0(rdhwr_ccres, tl)
+DEF_HELPER_1(pmon, void, int)
+DEF_HELPER_0(wait, void)
+
+#include "def-helper.h"
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 3fe62fb..390de7b 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -22,6 +22,7 @@
#include "host-utils.h"
+#include "helper.h"
/*****************************************************************************/
/* Exceptions processing helpers */
@@ -1659,6 +1660,26 @@ void r4k_do_tlbr (void)
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
+void do_tlbwi(void)
+{
+ env->tlb->do_tlbwi();
+}
+
+void do_tlbwr(void)
+{
+ env->tlb->do_tlbwr();
+}
+
+void do_tlbp(void)
+{
+ env->tlb->do_tlbp();
+}
+
+void do_tlbr(void)
+{
+ env->tlb->do_tlbr();
+}
+
/* Specials */
target_ulong do_di (void)
{
diff --git a/target-mips/translate.c b/target-mips/translate.c
index cefccb0..590c2b6 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -29,10 +29,13 @@
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
-#include "helper.h"
#include "tcg-op.h"
#include "qemu-common.h"
+#include "helper.h"
+#define GEN_HELPER 1
+#include "helper.h"
+
//#define MIPS_DEBUG_DISAS
//#define MIPS_DEBUG_SIGN_EXTENSIONS
//#define MIPS_SINGLE_STEP
@@ -423,101 +426,40 @@ enum {
};
/* global register indices */
-static TCGv cpu_env, cpu_gpr[32], cpu_PC;
+static TCGv_ptr cpu_env;
+static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, bcond, btarget;
-static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31;
+static TCGv cpu_dspctrl, btarget;
+static TCGv_i32 bcond;
+static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32];
+static TCGv_i64 fpu_fpr64[32];
+static TCGv_i32 fpu_fcr0, fpu_fcr31;
#include "gen-icount.h"
-static inline void tcg_gen_helper_0_i(void *func, uint32_t arg)
-
-{
- TCGv tmp = tcg_const_i32(arg);
-
- tcg_gen_helper_0_1(func, tmp);
- tcg_temp_free(tmp);
-}
-
-static inline void tcg_gen_helper_0_ii(void *func, uint32_t arg1, uint32_t arg2)
-{
- TCGv tmp1 = tcg_const_i32(arg1);
- TCGv tmp2 = tcg_const_i32(arg2);
-
- tcg_gen_helper_0_2(func, tmp1, tmp2);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
-}
-
-static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, uint32_t arg2)
-{
- TCGv tmp = tcg_const_i32(arg2);
-
- tcg_gen_helper_0_2(func, arg1, tmp);
- tcg_temp_free(tmp);
-}
-
-static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, uint32_t arg3)
-{
- TCGv tmp = tcg_const_i32(arg3);
-
- tcg_gen_helper_0_3(func, arg1, arg2, tmp);
- tcg_temp_free(tmp);
-}
-
-static inline void tcg_gen_helper_0_1ii(void *func, TCGv arg1, uint32_t arg2, uint32_t arg3)
-{
- TCGv tmp1 = tcg_const_i32(arg2);
- TCGv tmp2 = tcg_const_i32(arg3);
-
- tcg_gen_helper_0_3(func, arg1, tmp1, tmp2);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
-}
-
-static inline void tcg_gen_helper_1_i(void *func, TCGv ret, uint32_t arg)
-{
- TCGv tmp = tcg_const_i32(arg);
-
- tcg_gen_helper_1_1(func, ret, tmp);
- tcg_temp_free(tmp);
-}
-
-static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, uint32_t arg2)
-{
- TCGv tmp = tcg_const_i32(arg2);
-
- tcg_gen_helper_1_2(func, ret, arg1, tmp);
- tcg_temp_free(tmp);
-}
-
-static inline void tcg_gen_helper_1_1ii(void *func, TCGv ret, TCGv arg1, uint32_t arg2, uint32_t arg3)
-{
- TCGv tmp1 = tcg_const_i32(arg2);
- TCGv tmp2 = tcg_const_i32(arg3);
-
- tcg_gen_helper_1_3(func, ret, arg1, tmp1, tmp2);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
-}
-
-static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, uint32_t arg3)
-{
- TCGv tmp = tcg_const_i32(arg3);
+#define gen_helper_0i(name, arg) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg); \
+ gen_helper_##name(helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
- tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp);
- tcg_temp_free(tmp);
-}
+#define gen_helper_1i(name, arg1, arg2) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
+ gen_helper_##name(arg1, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
-static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, uint32_t arg3, uint32_t arg4)
-{
- TCGv tmp1 = tcg_const_i32(arg3);
- TCGv tmp2 = tcg_const_i32(arg4);
+#define gen_helper_2i(name, arg1, arg2, arg3) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
+ gen_helper_##name(arg1, arg2, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
- tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
-}
+#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
+ TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
+ gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
+ tcg_temp_free_i32(helper_tmp); \
+ } while(0)
typedef struct DisasContext {
struct TranslationBlock *tb;
@@ -618,21 +560,24 @@ static inline void gen_store_ACX (TCGv t, int reg)
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr (int from, int to)
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
if (from == 0)
tcg_gen_movi_tl(r_tmp1, 0);
else {
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+ TCGv_ptr addr = tcg_temp_new_ptr();
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
- tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
+ tcg_gen_ext_i32_ptr(addr, r_tmp2);
+ tcg_gen_add_ptr(addr, cpu_env, addr);
- tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from);
- tcg_temp_free(r_tmp2);
+ tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from);
+ tcg_temp_free_ptr(addr);
+ tcg_temp_free_i32(r_tmp2);
}
gen_store_gpr(r_tmp1, to);
tcg_temp_free(r_tmp1);
@@ -641,34 +586,37 @@ static inline void gen_load_srsgpr (int from, int to)
static inline void gen_store_srsgpr (int from, int to)
{
if (to != 0) {
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+ TCGv_ptr addr = tcg_temp_new_ptr();
gen_load_gpr(r_tmp1, from);
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
- tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
+ tcg_gen_ext_i32_ptr(addr, r_tmp2);
+ tcg_gen_add_ptr(addr, cpu_env, addr);
- tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to);
+ tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to);
+ tcg_temp_free_ptr(addr);
+ tcg_temp_free_i32(r_tmp2);
tcg_temp_free(r_tmp1);
- tcg_temp_free(r_tmp2);
}
}
/* Floating point register moves. */
-static inline void gen_load_fpr32 (TCGv t, int reg)
+static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
{
tcg_gen_mov_i32(t, fpu_fpr32[reg]);
}
-static inline void gen_store_fpr32 (TCGv t, int reg)
+static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
{
tcg_gen_mov_i32(fpu_fpr32[reg], t);
}
-static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
+static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64)
tcg_gen_mov_i64(t, fpu_fpr64[reg]);
@@ -677,7 +625,7 @@ static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
}
}
-static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg)
+static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64)
tcg_gen_mov_i64(fpu_fpr64[reg], t);
@@ -688,63 +636,61 @@ static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg)
}
}
-static inline void gen_load_fpr32h (TCGv t, int reg)
+static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
{
tcg_gen_mov_i32(t, fpu_fpr32h[reg]);
}
-static inline void gen_store_fpr32h (TCGv t, int reg)
+static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
{
tcg_gen_mov_i32(fpu_fpr32h[reg], t);
}
-static inline void get_fp_cond (TCGv t)
+static inline void get_fp_cond (TCGv_i32 t)
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 r_tmp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24);
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe);
tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23);
tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1);
tcg_gen_or_i32(t, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp1);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i32(r_tmp1);
+ tcg_temp_free_i32(r_tmp2);
}
-typedef void (fcmp_fun32)(uint32_t, uint32_t, int);
-typedef void (fcmp_fun64)(uint64_t, uint64_t, int);
-
-#define FOP_CONDS(fcmp_fun, type, fmt) \
-static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
- do_cmp ## type ## _ ## fmt ## _f, \
- do_cmp ## type ## _ ## fmt ## _un, \
- do_cmp ## type ## _ ## fmt ## _eq, \
- do_cmp ## type ## _ ## fmt ## _ueq, \
- do_cmp ## type ## _ ## fmt ## _olt, \
- do_cmp ## type ## _ ## fmt ## _ult, \
- do_cmp ## type ## _ ## fmt ## _ole, \
- do_cmp ## type ## _ ## fmt ## _ule, \
- do_cmp ## type ## _ ## fmt ## _sf, \
- do_cmp ## type ## _ ## fmt ## _ngle, \
- do_cmp ## type ## _ ## fmt ## _seq, \
- do_cmp ## type ## _ ## fmt ## _ngl, \
- do_cmp ## type ## _ ## fmt ## _lt, \
- do_cmp ## type ## _ ## fmt ## _nge, \
- do_cmp ## type ## _ ## fmt ## _le, \
- do_cmp ## type ## _ ## fmt ## _ngt, \
-}; \
-static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv a, TCGv b, int cc) \
+#define FOP_CONDS(type, fmt, bits) \
+static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
+ TCGv_i##bits b, int cc) \
{ \
- tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \
+ switch (n) { \
+ case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
+ case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
+ case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
+ case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
+ case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
+ case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
+ case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
+ case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
+ case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
+ case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
+ case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
+ case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
+ case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
+ case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
+ case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
+ case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
+ default: abort(); \
+ } \
}
-FOP_CONDS(fcmp_fun64, , d)
-FOP_CONDS(fcmp_fun64, abs, d)
-FOP_CONDS(fcmp_fun32, , s)
-FOP_CONDS(fcmp_fun32, abs, s)
-FOP_CONDS(fcmp_fun64, , ps)
-FOP_CONDS(fcmp_fun64, abs, ps)
+FOP_CONDS(, d, 64)
+FOP_CONDS(abs, d, 64)
+FOP_CONDS(, s, 32)
+FOP_CONDS(abs, s, 32)
+FOP_CONDS(, ps, 64)
+FOP_CONDS(abs, ps, 64)
#undef FOP_CONDS
/* Tests */
@@ -823,11 +769,11 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
ctx->saved_pc = ctx->pc;
}
if (ctx->hflags != ctx->saved_hflags) {
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(r_tmp, ctx->hflags);
tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
- tcg_temp_free(r_tmp);
+ tcg_temp_free_i32(r_tmp);
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
case MIPS_HFLAG_BR:
@@ -858,9 +804,13 @@ static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
static inline void
generate_exception_err (DisasContext *ctx, int excp, int err)
{
+ TCGv_i32 texcp = tcg_const_i32(excp);
+ TCGv_i32 terr = tcg_const_i32(err);
save_cpu_state(ctx, 1);
- tcg_gen_helper_0_ii(do_raise_exception_err, excp, err);
- tcg_gen_helper_0_0(do_interrupt_restart);
+ gen_helper_raise_exception_err(texcp, terr);
+ tcg_temp_free_i32(terr);
+ tcg_temp_free_i32(texcp);
+ gen_helper_interrupt_restart();
tcg_gen_exit_tb(0);
}
@@ -868,8 +818,8 @@ static inline void
generate_exception (DisasContext *ctx, int excp)
{
save_cpu_state(ctx, 1);
- tcg_gen_helper_0_i(do_raise_exception, excp);
- tcg_gen_helper_0_0(do_interrupt_restart);
+ gen_helper_0i(raise_exception, excp);
+ gen_helper_interrupt_restart();
tcg_gen_exit_tb(0);
}
@@ -999,7 +949,7 @@ OP_LD_ATOMIC(lld,ld64);
#define OP_ST_ATOMIC(insn,fname,almask) \
static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
{ \
- TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
+ TCGv r_tmp = tcg_temp_local_new(); \
int l1 = gen_new_label(); \
int l2 = gen_new_label(); \
int l3 = gen_new_label(); \
@@ -1030,8 +980,8 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
int base, int16_t offset)
{
const char *opn = "ldst";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
if (base == 0) {
tcg_gen_movi_tl(t0, offset);
@@ -1076,27 +1026,27 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LDL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_1_2i(do_ldl, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldl";
break;
case OPC_SDL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_0_2i(do_sdl, t0, t1, ctx->mem_idx);
+ gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
opn = "sdl";
break;
case OPC_LDR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_1_2i(do_ldr, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldr";
break;
case OPC_SDR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_0_2i(do_sdr, t0, t1, ctx->mem_idx);
+ gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
opn = "sdr";
break;
#endif
@@ -1143,27 +1093,27 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LWL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_1_2i(do_lwl, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwl";
break;
case OPC_SWL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_0_2i(do_swl, t0, t1, ctx->mem_idx);
+ gen_helper_2i(swl, t0, t1, ctx->mem_idx);
opn = "swr";
break;
case OPC_LWR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_1_2i(do_lwr, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwr";
break;
case OPC_SWR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- tcg_gen_helper_0_2i(do_swr, t0, t1, ctx->mem_idx);
+ gen_helper_2i(swr, t0, t1, ctx->mem_idx);
opn = "swr";
break;
case OPC_LL:
@@ -1194,14 +1144,14 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
int base, int16_t offset)
{
const char *opn = "flt_ldst";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
if (base == 0) {
tcg_gen_movi_tl(t0, offset);
} else if (offset == 0) {
gen_load_gpr(t0, base);
} else {
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t1 = tcg_temp_local_new();
gen_load_gpr(t0, base);
tcg_gen_movi_tl(t1, offset);
@@ -1213,41 +1163,47 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
switch (opc) {
case OPC_LWC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv t1 = tcg_temp_new();
- tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
+ tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
+ tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(fp0, ft);
- tcg_temp_free(fp0);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(fp0);
}
opn = "lwc1";
break;
case OPC_SWC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv t1 = tcg_temp_new();
gen_load_fpr32(fp0, ft);
- tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
- tcg_temp_free(fp0);
+ tcg_gen_extu_i32_tl(t1, fp0);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(fp0);
}
opn = "swc1";
break;
case OPC_LDC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
gen_store_fpr64(ctx, fp0, ft);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "ldc1";
break;
case OPC_SDC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "sdc1";
break;
@@ -1267,7 +1223,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
{
target_ulong uimm;
const char *opn = "imm arith";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
/* If no destination, treat it as a NOP.
@@ -1313,8 +1269,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_ADDI:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1343,8 +1299,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
#if defined(TARGET_MIPS64)
case OPC_DADDI:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1416,12 +1372,12 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
/* rotr is decoded as srl on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
if (uimm != 0) {
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(r_tmp1, t0);
tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
tcg_gen_ext_i32_tl(t0, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i32(r_tmp1);
}
opn = "rotr";
} else {
@@ -1520,8 +1476,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "arith";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
&& opc != OPC_DADD && opc != OPC_DSUB) {
@@ -1541,8 +1497,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_ADD:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1572,8 +1528,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_SUB:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1603,8 +1559,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
#if defined(TARGET_MIPS64)
case OPC_DADD:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1630,8 +1586,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_DSUB:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv r_tmp1 = tcg_temp_new();
+ TCGv r_tmp2 = tcg_temp_new();
int l1 = gen_new_label();
save_cpu_state(ctx, 1);
@@ -1735,14 +1691,14 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_andi_tl(t0, t0, 0x1f);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 r_tmp2 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(r_tmp1, t0);
tcg_gen_trunc_tl_i32(r_tmp2, t1);
tcg_gen_rotr_i32(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp1);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i32(r_tmp1);
+ tcg_temp_free_i32(r_tmp2);
tcg_gen_br(l2);
}
gen_set_label(l1);
@@ -1827,7 +1783,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
{
const char *opn = "hilo";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
@@ -1869,8 +1825,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
int rs, int rt)
{
const char *opn = "mul/div";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
@@ -1882,9 +1838,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
{
int l2 = gen_new_label();
- TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv r_tmp2 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv r_tmp3 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_local_new_i32();
+ TCGv_i32 r_tmp2 = tcg_temp_local_new_i32();
+ TCGv_i32 r_tmp3 = tcg_temp_local_new_i32();
tcg_gen_trunc_tl_i32(r_tmp1, t0);
tcg_gen_trunc_tl_i32(r_tmp2, t1);
@@ -1898,9 +1854,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_rem_i32(r_tmp2, r_tmp1, r_tmp2);
tcg_gen_ext_i32_tl(cpu_LO[0], r_tmp3);
tcg_gen_ext_i32_tl(cpu_HI[0], r_tmp2);
- tcg_temp_free(r_tmp1);
- tcg_temp_free(r_tmp2);
- tcg_temp_free(r_tmp3);
+ tcg_temp_free_i32(r_tmp1);
+ tcg_temp_free_i32(r_tmp2);
+ tcg_temp_free_i32(r_tmp3);
}
gen_set_label(l1);
}
@@ -1913,9 +1869,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_ext32s_tl(t1, t1);
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+ TCGv_i32 r_tmp3 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(r_tmp1, t0);
tcg_gen_trunc_tl_i32(r_tmp2, t1);
@@ -1923,9 +1879,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_ext_i32_tl(cpu_LO[0], r_tmp3);
tcg_gen_ext_i32_tl(cpu_HI[0], r_tmp1);
- tcg_temp_free(r_tmp1);
- tcg_temp_free(r_tmp2);
- tcg_temp_free(r_tmp3);
+ tcg_temp_free_i32(r_tmp1);
+ tcg_temp_free_i32(r_tmp2);
+ tcg_temp_free_i32(r_tmp3);
}
gen_set_label(l1);
}
@@ -1933,17 +1889,17 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break;
case OPC_MULT:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(r_tmp1, t0);
tcg_gen_ext_tl_i64(r_tmp2, t1);
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_HI[0], t1);
}
@@ -1951,19 +1907,19 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break;
case OPC_MULTU:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_extu_tl_i64(r_tmp1, t0);
tcg_gen_extu_tl_i64(r_tmp2, t1);
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_HI[0], t1);
}
@@ -2003,29 +1959,29 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
opn = "ddivu";
break;
case OPC_DMULT:
- tcg_gen_helper_0_2(do_dmult, t0, t1);
+ gen_helper_dmult(t0, t1);
opn = "dmult";
break;
case OPC_DMULTU:
- tcg_gen_helper_0_2(do_dmultu, t0, t1);
+ gen_helper_dmultu(t0, t1);
opn = "dmultu";
break;
#endif
case OPC_MADD:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(r_tmp1, t0);
tcg_gen_ext_tl_i64(r_tmp2, t1);
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_LO[1], t1);
}
@@ -2033,8 +1989,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break;
case OPC_MADDU:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2043,11 +1999,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_HI[0], t1);
}
@@ -2055,19 +2011,19 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break;
case OPC_MSUB:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(r_tmp1, t0);
tcg_gen_ext_tl_i64(r_tmp2, t1);
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_HI[0], t1);
}
@@ -2075,8 +2031,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break;
case OPC_MSUBU:
{
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 r_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 r_tmp2 = tcg_temp_new_i64();
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2085,11 +2041,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_gen_concat_tl_i64(r_tmp2, cpu_LO[0], cpu_HI[0]);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
- tcg_temp_free(r_tmp2);
+ tcg_temp_free_i64(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
tcg_gen_trunc_i64_tl(t1, r_tmp1);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i64(r_tmp1);
tcg_gen_ext32s_tl(cpu_LO[0], t0);
tcg_gen_ext32s_tl(cpu_HI[0], t1);
}
@@ -2110,67 +2066,67 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "mul vr54xx";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
switch (opc) {
case OPC_VR54XX_MULS:
- tcg_gen_helper_1_2(do_muls, t0, t0, t1);
+ gen_helper_muls(t0, t0, t1);
opn = "muls";
break;
case OPC_VR54XX_MULSU:
- tcg_gen_helper_1_2(do_mulsu, t0, t0, t1);
+ gen_helper_mulsu(t0, t0, t1);
opn = "mulsu";
break;
case OPC_VR54XX_MACC:
- tcg_gen_helper_1_2(do_macc, t0, t0, t1);
+ gen_helper_macc(t0, t0, t1);
opn = "macc";
break;
case OPC_VR54XX_MACCU:
- tcg_gen_helper_1_2(do_maccu, t0, t0, t1);
+ gen_helper_maccu(t0, t0, t1);
opn = "maccu";
break;
case OPC_VR54XX_MSAC:
- tcg_gen_helper_1_2(do_msac, t0, t0, t1);
+ gen_helper_msac(t0, t0, t1);
opn = "msac";
break;
case OPC_VR54XX_MSACU:
- tcg_gen_helper_1_2(do_msacu, t0, t0, t1);
+ gen_helper_msacu(t0, t0, t1);
opn = "msacu";
break;
case OPC_VR54XX_MULHI:
- tcg_gen_helper_1_2(do_mulhi, t0, t0, t1);
+ gen_helper_mulhi(t0, t0, t1);
opn = "mulhi";
break;
case OPC_VR54XX_MULHIU:
- tcg_gen_helper_1_2(do_mulhiu, t0, t0, t1);
+ gen_helper_mulhiu(t0, t0, t1);
opn = "mulhiu";
break;
case OPC_VR54XX_MULSHI:
- tcg_gen_helper_1_2(do_mulshi, t0, t0, t1);
+ gen_helper_mulshi(t0, t0, t1);
opn = "mulshi";
break;
case OPC_VR54XX_MULSHIU:
- tcg_gen_helper_1_2(do_mulshiu, t0, t0, t1);
+ gen_helper_mulshiu(t0, t0, t1);
opn = "mulshiu";
break;
case OPC_VR54XX_MACCHI:
- tcg_gen_helper_1_2(do_macchi, t0, t0, t1);
+ gen_helper_macchi(t0, t0, t1);
opn = "macchi";
break;
case OPC_VR54XX_MACCHIU:
- tcg_gen_helper_1_2(do_macchiu, t0, t0, t1);
+ gen_helper_macchiu(t0, t0, t1);
opn = "macchiu";
break;
case OPC_VR54XX_MSACHI:
- tcg_gen_helper_1_2(do_msachi, t0, t0, t1);
+ gen_helper_msachi(t0, t0, t1);
opn = "msachi";
break;
case OPC_VR54XX_MSACHIU:
- tcg_gen_helper_1_2(do_msachiu, t0, t0, t1);
+ gen_helper_msachiu(t0, t0, t1);
opn = "msachiu";
break;
default:
@@ -2190,7 +2146,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
const char *opn = "CLx";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
if (rd == 0) {
/* Treat as NOP. */
@@ -2200,20 +2156,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rs);
switch (opc) {
case OPC_CLO:
- tcg_gen_helper_1_1(do_clo, t0, t0);
+ gen_helper_clo(t0, t0);
opn = "clo";
break;
case OPC_CLZ:
- tcg_gen_helper_1_1(do_clz, t0, t0);
+ gen_helper_clz(t0, t0);
opn = "clz";
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
- tcg_gen_helper_1_1(do_dclo, t0, t0);
+ gen_helper_dclo(t0, t0);
opn = "dclo";
break;
case OPC_DCLZ:
- tcg_gen_helper_1_1(do_dclz, t0, t0);
+ gen_helper_dclz(t0, t0);
opn = "dclz";
break;
#endif
@@ -2234,8 +2190,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
int rs, int rt, int16_t imm)
{
int cond;
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
cond = 0;
/* Load needed operands */
@@ -2328,7 +2284,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
int l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
- tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP);
+ gen_helper_0i(raise_exception, EXCP_TRAP);
gen_set_label(l1);
}
ctx->bstate = BS_STOP;
@@ -2358,8 +2314,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
target_ulong btgt = -1;
int blink = 0;
int bcond_compute = 0;
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
@@ -2600,8 +2556,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
{
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
target_ulong mask;
gen_load_gpr(t1, rs);
@@ -2691,8 +2647,8 @@ fail:
static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
{
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
switch (op2) {
@@ -2747,11 +2703,11 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
/* CP0 (MMU and control) */
static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
{
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp = tcg_temp_new_i32();
tcg_gen_ld_i32(r_tmp, cpu_env, off);
tcg_gen_ext_i32_tl(t, r_tmp);
- tcg_temp_free(r_tmp);
+ tcg_temp_free_i32(r_tmp);
}
static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
@@ -2762,11 +2718,11 @@ static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
{
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(r_tmp, t);
tcg_gen_st_i32(r_tmp, cpu_env, off);
- tcg_temp_free(r_tmp);
+ tcg_temp_free_i32(r_tmp);
}
static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
@@ -2791,17 +2747,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
+ gen_helper_mfc0_mvpcontrol(t0);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
+ gen_helper_mfc0_mvpconf0(t0);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
+ gen_helper_mfc0_mvpconf1(t0);
rn = "MVPConf1";
break;
default:
@@ -2811,7 +2767,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 1:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mfc0_random, t0);
+ gen_helper_mfc0_random(t0);
rn = "Random";
break;
case 1:
@@ -2862,37 +2818,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
+ gen_helper_mfc0_tcstatus(t0);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
+ gen_helper_mfc0_tcbind(t0);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcrestart, t0);
+ gen_helper_mfc0_tcrestart(t0);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tchalt, t0);
+ gen_helper_mfc0_tchalt(t0);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tccontext, t0);
+ gen_helper_mfc0_tccontext(t0);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcschedule, t0);
+ gen_helper_mfc0_tcschedule(t0);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcschefback, t0);
+ gen_helper_mfc0_tcschefback(t0);
rn = "TCScheFBack";
break;
default:
@@ -2918,7 +2874,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
rn = "Context";
break;
case 1:
-// tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
+// gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -3003,7 +2959,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- tcg_gen_helper_1_0(do_mfc0_count, t0);
+ gen_helper_mfc0_count(t0);
if (use_icount) {
gen_io_end();
ctx->bstate = BS_STOP;
@@ -3133,7 +3089,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 17:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mfc0_lladdr, t0);
+ gen_helper_mfc0_lladdr(t0);
rn = "LLAddr";
break;
default:
@@ -3143,7 +3099,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 18:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_1_i(do_mfc0_watchlo, t0, sel);
+ gen_helper_1i(mfc0_watchlo, t0, sel);
rn = "WatchLo";
break;
default:
@@ -3153,7 +3109,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 19:
switch (sel) {
case 0 ...7:
- tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
+ gen_helper_1i(mfc0_watchhi, t0, sel);
rn = "WatchHi";
break;
default:
@@ -3192,23 +3148,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
+ gen_helper_mfc0_debug(t0); /* EJTAG support */
rn = "Debug";
break;
case 1:
-// tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
+// gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
rn = "TraceControl";
// break;
case 2:
-// tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
+// gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
rn = "TraceControl2";
// break;
case 3:
-// tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
+// gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
rn = "UserTraceData";
// break;
case 4:
-// tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
+// gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
rn = "TraceBPC";
// break;
default:
@@ -3234,31 +3190,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
rn = "Performance0";
break;
case 1:
-// tcg_gen_helper_1_0(do_mfc0_performance1, t0);
+// gen_helper_mfc0_performance1(t0);
rn = "Performance1";
// break;
case 2:
-// tcg_gen_helper_1_0(do_mfc0_performance2, t0);
+// gen_helper_mfc0_performance2(t0);
rn = "Performance2";
// break;
case 3:
-// tcg_gen_helper_1_0(do_mfc0_performance3, t0);
+// gen_helper_mfc0_performance3(t0);
rn = "Performance3";
// break;
case 4:
-// tcg_gen_helper_1_0(do_mfc0_performance4, t0);
+// gen_helper_mfc0_performance4(t0);
rn = "Performance4";
// break;
case 5:
-// tcg_gen_helper_1_0(do_mfc0_performance5, t0);
+// gen_helper_mfc0_performance5(t0);
rn = "Performance5";
// break;
case 6:
-// tcg_gen_helper_1_0(do_mfc0_performance6, t0);
+// gen_helper_mfc0_performance6(t0);
rn = "Performance6";
// break;
case 7:
-// tcg_gen_helper_1_0(do_mfc0_performance7, t0);
+// gen_helper_mfc0_performance7(t0);
rn = "Performance7";
// break;
default:
@@ -3376,12 +3332,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 0:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_index, t0);
+ gen_helper_mtc0_index(t0);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
+ gen_helper_mtc0_mvpcontrol(t0);
rn = "MVPControl";
break;
case 2:
@@ -3406,22 +3362,22 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
+ gen_helper_mtc0_vpecontrol(t0);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
+ gen_helper_mtc0_vpeconf0(t0);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
+ gen_helper_mtc0_vpeconf1(t0);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
+ gen_helper_mtc0_yqmask(t0);
rn = "YQMask";
break;
case 5:
@@ -3436,7 +3392,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
+ gen_helper_mtc0_vpeopt(t0);
rn = "VPEOpt";
break;
default:
@@ -3446,42 +3402,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 2:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
+ gen_helper_mtc0_entrylo0(t0);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
+ gen_helper_mtc0_tcstatus(t0);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
+ gen_helper_mtc0_tcbind(t0);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
+ gen_helper_mtc0_tcrestart(t0);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
+ gen_helper_mtc0_tchalt(t0);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
+ gen_helper_mtc0_tccontext(t0);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
+ gen_helper_mtc0_tcschedule(t0);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
+ gen_helper_mtc0_tcschefback(t0);
rn = "TCScheFBack";
break;
default:
@@ -3491,7 +3447,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 3:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
+ gen_helper_mtc0_entrylo1(t0);
rn = "EntryLo1";
break;
default:
@@ -3501,11 +3457,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 4:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_context, t0);
+ gen_helper_mtc0_context(t0);
rn = "Context";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -3515,12 +3471,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 5:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
+ gen_helper_mtc0_pagemask(t0);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
+ gen_helper_mtc0_pagegrain(t0);
rn = "PageGrain";
break;
default:
@@ -3530,32 +3486,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 6:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_wired, t0);
+ gen_helper_mtc0_wired(t0);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
+ gen_helper_mtc0_srsconf0(t0);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
+ gen_helper_mtc0_srsconf1(t0);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
+ gen_helper_mtc0_srsconf2(t0);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
+ gen_helper_mtc0_srsconf3(t0);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
+ gen_helper_mtc0_srsconf4(t0);
rn = "SRSConf4";
break;
default:
@@ -3566,7 +3522,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
+ gen_helper_mtc0_hwrena(t0);
rn = "HWREna";
break;
default:
@@ -3580,7 +3536,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 9:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_count, t0);
+ gen_helper_mtc0_count(t0);
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -3593,7 +3549,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 10:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
+ gen_helper_mtc0_entryhi(t0);
rn = "EntryHi";
break;
default:
@@ -3603,7 +3559,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 11:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_compare, t0);
+ gen_helper_mtc0_compare(t0);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -3616,7 +3572,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 12:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_status, t0);
+ gen_helper_mtc0_status(t0);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
@@ -3624,14 +3580,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_intctl, t0);
+ gen_helper_mtc0_intctl(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
+ gen_helper_mtc0_srsctl(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
@@ -3650,7 +3606,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 13:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_cause, t0);
+ gen_helper_mtc0_cause(t0);
rn = "Cause";
break;
default:
@@ -3677,7 +3633,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_ebase, t0);
+ gen_helper_mtc0_ebase(t0);
rn = "EBase";
break;
default:
@@ -3687,7 +3643,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 16:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_config0, t0);
+ gen_helper_mtc0_config0(t0);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -3697,7 +3653,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
rn = "Config1";
break;
case 2:
- tcg_gen_helper_0_1(do_mtc0_config2, t0);
+ gen_helper_mtc0_config2(t0);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -3734,7 +3690,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 18:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
+ gen_helper_1i(mtc0_watchlo, t0, sel);
rn = "WatchLo";
break;
default:
@@ -3744,7 +3700,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 19:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
+ gen_helper_1i(mtc0_watchhi, t0, sel);
rn = "WatchHi";
break;
default:
@@ -3756,7 +3712,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
+ gen_helper_mtc0_xcontext(t0);
rn = "XContext";
break;
#endif
@@ -3768,7 +3724,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_framemask, t0);
+ gen_helper_mtc0_framemask(t0);
rn = "Framemask";
break;
default:
@@ -3782,20 +3738,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
+ gen_helper_mtc0_debug(t0); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 2:
-// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -3803,13 +3759,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 3:
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 4:
-// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
@@ -3832,35 +3788,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 25:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_performance0, t0);
+ gen_helper_mtc0_performance0(t0);
rn = "Performance0";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
+// gen_helper_mtc0_performance1(t0);
rn = "Performance1";
// break;
case 2:
-// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
+// gen_helper_mtc0_performance2(t0);
rn = "Performance2";
// break;
case 3:
-// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
+// gen_helper_mtc0_performance3(t0);
rn = "Performance3";
// break;
case 4:
-// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
+// gen_helper_mtc0_performance4(t0);
rn = "Performance4";
// break;
case 5:
-// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
+// gen_helper_mtc0_performance5(t0);
rn = "Performance5";
// break;
case 6:
-// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
+// gen_helper_mtc0_performance6(t0);
rn = "Performance6";
// break;
case 7:
-// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
+// gen_helper_mtc0_performance7(t0);
rn = "Performance7";
// break;
default:
@@ -3887,14 +3843,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 2:
case 4:
case 6:
- tcg_gen_helper_0_1(do_mtc0_taglo, t0);
+ gen_helper_mtc0_taglo(t0);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- tcg_gen_helper_0_1(do_mtc0_datalo, t0);
+ gen_helper_mtc0_datalo(t0);
rn = "DataLo";
break;
default:
@@ -3907,14 +3863,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
case 2:
case 4:
case 6:
- tcg_gen_helper_0_1(do_mtc0_taghi, t0);
+ gen_helper_mtc0_taghi(t0);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- tcg_gen_helper_0_1(do_mtc0_datahi, t0);
+ gen_helper_mtc0_datahi(t0);
rn = "DataHi";
break;
default:
@@ -3988,17 +3944,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
+ gen_helper_mfc0_mvpcontrol(t0);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
+ gen_helper_mfc0_mvpconf0(t0);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
+ gen_helper_mfc0_mvpconf1(t0);
rn = "MVPConf1";
break;
default:
@@ -4008,7 +3964,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 1:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mfc0_random, t0);
+ gen_helper_mfc0_random(t0);
rn = "Random";
break;
case 1:
@@ -4058,37 +4014,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
+ gen_helper_mfc0_tcstatus(t0);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
+ gen_helper_mfc0_tcbind(t0);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_dmfc0_tcrestart, t0);
+ gen_helper_dmfc0_tcrestart(t0);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_dmfc0_tchalt, t0);
+ gen_helper_dmfc0_tchalt(t0);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_dmfc0_tccontext, t0);
+ gen_helper_dmfc0_tccontext(t0);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_dmfc0_tcschedule, t0);
+ gen_helper_dmfc0_tcschedule(t0);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_0(do_dmfc0_tcschefback, t0);
+ gen_helper_dmfc0_tcschefback(t0);
rn = "TCScheFBack";
break;
default:
@@ -4112,7 +4068,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
rn = "Context";
break;
case 1:
-// tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
+// gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -4196,7 +4152,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- tcg_gen_helper_1_0(do_mfc0_count, t0);
+ gen_helper_mfc0_count(t0);
if (use_icount) {
gen_io_end();
ctx->bstate = BS_STOP;
@@ -4323,7 +4279,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 17:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_dmfc0_lladdr, t0);
+ gen_helper_dmfc0_lladdr(t0);
rn = "LLAddr";
break;
default:
@@ -4333,7 +4289,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 18:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_1_i(do_dmfc0_watchlo, t0, sel);
+ gen_helper_1i(dmfc0_watchlo, t0, sel);
rn = "WatchLo";
break;
default:
@@ -4343,7 +4299,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 19:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
+ gen_helper_1i(mfc0_watchhi, t0, sel);
rn = "WatchHi";
break;
default:
@@ -4379,23 +4335,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
+ gen_helper_mfc0_debug(t0); /* EJTAG support */
rn = "Debug";
break;
case 1:
-// tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
rn = "TraceControl";
// break;
case 2:
-// tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
rn = "TraceControl2";
// break;
case 3:
-// tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
+// gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
rn = "UserTraceData";
// break;
case 4:
-// tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
+// gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
rn = "TraceBPC";
// break;
default:
@@ -4420,31 +4376,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
rn = "Performance0";
break;
case 1:
-// tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
+// gen_helper_dmfc0_performance1(t0);
rn = "Performance1";
// break;
case 2:
-// tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
+// gen_helper_dmfc0_performance2(t0);
rn = "Performance2";
// break;
case 3:
-// tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
+// gen_helper_dmfc0_performance3(t0);
rn = "Performance3";
// break;
case 4:
-// tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
+// gen_helper_dmfc0_performance4(t0);
rn = "Performance4";
// break;
case 5:
-// tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
+// gen_helper_dmfc0_performance5(t0);
rn = "Performance5";
// break;
case 6:
-// tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
+// gen_helper_dmfc0_performance6(t0);
rn = "Performance6";
// break;
case 7:
-// tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
+// gen_helper_dmfc0_performance7(t0);
rn = "Performance7";
// break;
default:
@@ -4562,12 +4518,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 0:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_index, t0);
+ gen_helper_mtc0_index(t0);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
+ gen_helper_mtc0_mvpcontrol(t0);
rn = "MVPControl";
break;
case 2:
@@ -4592,22 +4548,22 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
+ gen_helper_mtc0_vpecontrol(t0);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
+ gen_helper_mtc0_vpeconf0(t0);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
+ gen_helper_mtc0_vpeconf1(t0);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
+ gen_helper_mtc0_yqmask(t0);
rn = "YQMask";
break;
case 5:
@@ -4622,7 +4578,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
+ gen_helper_mtc0_vpeopt(t0);
rn = "VPEOpt";
break;
default:
@@ -4632,42 +4588,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 2:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
+ gen_helper_mtc0_entrylo0(t0);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
+ gen_helper_mtc0_tcstatus(t0);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
+ gen_helper_mtc0_tcbind(t0);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
+ gen_helper_mtc0_tcrestart(t0);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
+ gen_helper_mtc0_tchalt(t0);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
+ gen_helper_mtc0_tccontext(t0);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
+ gen_helper_mtc0_tcschedule(t0);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
+ gen_helper_mtc0_tcschefback(t0);
rn = "TCScheFBack";
break;
default:
@@ -4677,7 +4633,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 3:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
+ gen_helper_mtc0_entrylo1(t0);
rn = "EntryLo1";
break;
default:
@@ -4687,11 +4643,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 4:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_context, t0);
+ gen_helper_mtc0_context(t0);
rn = "Context";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
@@ -4701,12 +4657,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 5:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
+ gen_helper_mtc0_pagemask(t0);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
+ gen_helper_mtc0_pagegrain(t0);
rn = "PageGrain";
break;
default:
@@ -4716,32 +4672,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 6:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_wired, t0);
+ gen_helper_mtc0_wired(t0);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
+ gen_helper_mtc0_srsconf0(t0);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
+ gen_helper_mtc0_srsconf1(t0);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
+ gen_helper_mtc0_srsconf2(t0);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
+ gen_helper_mtc0_srsconf3(t0);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
+ gen_helper_mtc0_srsconf4(t0);
rn = "SRSConf4";
break;
default:
@@ -4752,7 +4708,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
+ gen_helper_mtc0_hwrena(t0);
rn = "HWREna";
break;
default:
@@ -4766,7 +4722,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 9:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_count, t0);
+ gen_helper_mtc0_count(t0);
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -4779,7 +4735,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 10:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
+ gen_helper_mtc0_entryhi(t0);
rn = "EntryHi";
break;
default:
@@ -4789,7 +4745,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 11:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_compare, t0);
+ gen_helper_mtc0_compare(t0);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -4802,7 +4758,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 12:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_status, t0);
+ gen_helper_mtc0_status(t0);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
@@ -4810,14 +4766,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_intctl, t0);
+ gen_helper_mtc0_intctl(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
+ gen_helper_mtc0_srsctl(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
@@ -4836,7 +4792,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 13:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_cause, t0);
+ gen_helper_mtc0_cause(t0);
rn = "Cause";
break;
default:
@@ -4863,7 +4819,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- tcg_gen_helper_0_1(do_mtc0_ebase, t0);
+ gen_helper_mtc0_ebase(t0);
rn = "EBase";
break;
default:
@@ -4873,7 +4829,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 16:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_config0, t0);
+ gen_helper_mtc0_config0(t0);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -4883,7 +4839,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
rn = "Config1";
break;
case 2:
- tcg_gen_helper_0_1(do_mtc0_config2, t0);
+ gen_helper_mtc0_config2(t0);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -4911,7 +4867,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 18:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
+ gen_helper_1i(mtc0_watchlo, t0, sel);
rn = "WatchLo";
break;
default:
@@ -4921,7 +4877,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 19:
switch (sel) {
case 0 ... 7:
- tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
+ gen_helper_1i(mtc0_watchhi, t0, sel);
rn = "WatchHi";
break;
default:
@@ -4932,7 +4888,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
+ gen_helper_mtc0_xcontext(t0);
rn = "XContext";
break;
default:
@@ -4943,7 +4899,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_framemask, t0);
+ gen_helper_mtc0_framemask(t0);
rn = "Framemask";
break;
default:
@@ -4957,32 +4913,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
+ gen_helper_mtc0_debug(t0); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl";
// break;
case 2:
-// tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl2";
// break;
case 3:
-// tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "UserTraceData";
// break;
case 4:
-// tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
@@ -5005,35 +4961,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 25:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mtc0_performance0, t0);
+ gen_helper_mtc0_performance0(t0);
rn = "Performance0";
break;
case 1:
-// tcg_gen_helper_0_1(do_mtc0_performance1, t0);
+// gen_helper_mtc0_performance1(t0);
rn = "Performance1";
// break;
case 2:
-// tcg_gen_helper_0_1(do_mtc0_performance2, t0);
+// gen_helper_mtc0_performance2(t0);
rn = "Performance2";
// break;
case 3:
-// tcg_gen_helper_0_1(do_mtc0_performance3, t0);
+// gen_helper_mtc0_performance3(t0);
rn = "Performance3";
// break;
case 4:
-// tcg_gen_helper_0_1(do_mtc0_performance4, t0);
+// gen_helper_mtc0_performance4(t0);
rn = "Performance4";
// break;
case 5:
-// tcg_gen_helper_0_1(do_mtc0_performance5, t0);
+// gen_helper_mtc0_performance5(t0);
rn = "Performance5";
// break;
case 6:
-// tcg_gen_helper_0_1(do_mtc0_performance6, t0);
+// gen_helper_mtc0_performance6(t0);
rn = "Performance6";
// break;
case 7:
-// tcg_gen_helper_0_1(do_mtc0_performance7, t0);
+// gen_helper_mtc0_performance7(t0);
rn = "Performance7";
// break;
default:
@@ -5060,14 +5016,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 2:
case 4:
case 6:
- tcg_gen_helper_0_1(do_mtc0_taglo, t0);
+ gen_helper_mtc0_taglo(t0);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- tcg_gen_helper_0_1(do_mtc0_datalo, t0);
+ gen_helper_mtc0_datalo(t0);
rn = "DataLo";
break;
default:
@@ -5080,14 +5036,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
case 2:
case 4:
case 6:
- tcg_gen_helper_0_1(do_mtc0_taghi, t0);
+ gen_helper_mtc0_taghi(t0);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- tcg_gen_helper_0_1(do_mtc0_datahi, t0);
+ gen_helper_mtc0_datahi(t0);
rn = "DataHi";
break;
default:
@@ -5149,7 +5105,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
@@ -5163,25 +5119,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
case 2:
switch (sel) {
case 1:
- tcg_gen_helper_1_0(do_mftc0_tcstatus, t0);
+ gen_helper_mftc0_tcstatus(t0);
break;
case 2:
- tcg_gen_helper_1_0(do_mftc0_tcbind, t0);
+ gen_helper_mftc0_tcbind(t0);
break;
case 3:
- tcg_gen_helper_1_0(do_mftc0_tcrestart, t0);
+ gen_helper_mftc0_tcrestart(t0);
break;
case 4:
- tcg_gen_helper_1_0(do_mftc0_tchalt, t0);
+ gen_helper_mftc0_tchalt(t0);
break;
case 5:
- tcg_gen_helper_1_0(do_mftc0_tccontext, t0);
+ gen_helper_mftc0_tccontext(t0);
break;
case 6:
- tcg_gen_helper_1_0(do_mftc0_tcschedule, t0);
+ gen_helper_mftc0_tcschedule(t0);
break;
case 7:
- tcg_gen_helper_1_0(do_mftc0_tcschefback, t0);
+ gen_helper_mftc0_tcschefback(t0);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5191,7 +5147,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
case 10:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mftc0_entryhi, t0);
+ gen_helper_mftc0_entryhi(t0);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5200,7 +5156,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
case 12:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mftc0_status, t0);
+ gen_helper_mftc0_status(t0);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5209,7 +5165,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_1_0(do_mftc0_debug, t0);
+ gen_helper_mftc0_debug(t0);
break;
default:
gen_mfc0(env, ctx, t0, rt, sel);
@@ -5222,49 +5178,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
} else switch (sel) {
/* GPR registers. */
case 0:
- tcg_gen_helper_1_i(do_mftgpr, t0, rt);
+ gen_helper_1i(mftgpr, t0, rt);
break;
/* Auxiliary CPU registers */
case 1:
switch (rt) {
case 0:
- tcg_gen_helper_1_i(do_mftlo, t0, 0);
+ gen_helper_1i(mftlo, t0, 0);
break;
case 1:
- tcg_gen_helper_1_i(do_mfthi, t0, 0);
+ gen_helper_1i(mfthi, t0, 0);
break;
case 2:
- tcg_gen_helper_1_i(do_mftacx, t0, 0);
+ gen_helper_1i(mftacx, t0, 0);
break;
case 4:
- tcg_gen_helper_1_i(do_mftlo, t0, 1);
+ gen_helper_1i(mftlo, t0, 1);
break;
case 5:
- tcg_gen_helper_1_i(do_mfthi, t0, 1);
+ gen_helper_1i(mfthi, t0, 1);
break;
case 6:
- tcg_gen_helper_1_i(do_mftacx, t0, 1);
+ gen_helper_1i(mftacx, t0, 1);
break;
case 8:
- tcg_gen_helper_1_i(do_mftlo, t0, 2);
+ gen_helper_1i(mftlo, t0, 2);
break;
case 9:
- tcg_gen_helper_1_i(do_mfthi, t0, 2);
+ gen_helper_1i(mfthi, t0, 2);
break;
case 10:
- tcg_gen_helper_1_i(do_mftacx, t0, 2);
+ gen_helper_1i(mftacx, t0, 2);
break;
case 12:
- tcg_gen_helper_1_i(do_mftlo, t0, 3);
+ gen_helper_1i(mftlo, t0, 3);
break;
case 13:
- tcg_gen_helper_1_i(do_mfthi, t0, 3);
+ gen_helper_1i(mfthi, t0, 3);
break;
case 14:
- tcg_gen_helper_1_i(do_mftacx, t0, 3);
+ gen_helper_1i(mftacx, t0, 3);
break;
case 16:
- tcg_gen_helper_1_0(do_mftdsp, t0);
+ gen_helper_mftdsp(t0);
break;
default:
goto die;
@@ -5274,22 +5230,22 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
case 2:
/* XXX: For now we support only a single FPU context. */
if (h == 0) {
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
} else {
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, rt);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- tcg_gen_helper_1_1i(do_cfc1, t0, t0, rt);
+ gen_helper_1i(cfc1, t0, rt);
break;
/* COP2: Not implemented. */
case 4:
@@ -5323,7 +5279,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
@@ -5338,25 +5294,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
case 2:
switch (sel) {
case 1:
- tcg_gen_helper_0_1(do_mttc0_tcstatus, t0);
+ gen_helper_mttc0_tcstatus(t0);
break;
case 2:
- tcg_gen_helper_0_1(do_mttc0_tcbind, t0);
+ gen_helper_mttc0_tcbind(t0);
break;
case 3:
- tcg_gen_helper_0_1(do_mttc0_tcrestart, t0);
+ gen_helper_mttc0_tcrestart(t0);
break;
case 4:
- tcg_gen_helper_0_1(do_mttc0_tchalt, t0);
+ gen_helper_mttc0_tchalt(t0);
break;
case 5:
- tcg_gen_helper_0_1(do_mttc0_tccontext, t0);
+ gen_helper_mttc0_tccontext(t0);
break;
case 6:
- tcg_gen_helper_0_1(do_mttc0_tcschedule, t0);
+ gen_helper_mttc0_tcschedule(t0);
break;
case 7:
- tcg_gen_helper_0_1(do_mttc0_tcschefback, t0);
+ gen_helper_mttc0_tcschefback(t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5366,7 +5322,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
case 10:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mttc0_entryhi, t0);
+ gen_helper_mttc0_entryhi(t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5375,7 +5331,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
case 12:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mttc0_status, t0);
+ gen_helper_mttc0_status(t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5384,7 +5340,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
case 23:
switch (sel) {
case 0:
- tcg_gen_helper_0_1(do_mttc0_debug, t0);
+ gen_helper_mttc0_debug(t0);
break;
default:
gen_mtc0(env, ctx, t0, rd, sel);
@@ -5397,49 +5353,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
} else switch (sel) {
/* GPR registers. */
case 0:
- tcg_gen_helper_0_1i(do_mttgpr, t0, rd);
+ gen_helper_1i(mttgpr, t0, rd);
break;
/* Auxiliary CPU registers */
case 1:
switch (rd) {
case 0:
- tcg_gen_helper_0_1i(do_mttlo, t0, 0);
+ gen_helper_1i(mttlo, t0, 0);
break;
case 1:
- tcg_gen_helper_0_1i(do_mtthi, t0, 0);
+ gen_helper_1i(mtthi, t0, 0);
break;
case 2:
- tcg_gen_helper_0_1i(do_mttacx, t0, 0);
+ gen_helper_1i(mttacx, t0, 0);
break;
case 4:
- tcg_gen_helper_0_1i(do_mttlo, t0, 1);
+ gen_helper_1i(mttlo, t0, 1);
break;
case 5:
- tcg_gen_helper_0_1i(do_mtthi, t0, 1);
+ gen_helper_1i(mtthi, t0, 1);
break;
case 6:
- tcg_gen_helper_0_1i(do_mttacx, t0, 1);
+ gen_helper_1i(mttacx, t0, 1);
break;
case 8:
- tcg_gen_helper_0_1i(do_mttlo, t0, 2);
+ gen_helper_1i(mttlo, t0, 2);
break;
case 9:
- tcg_gen_helper_0_1i(do_mtthi, t0, 2);
+ gen_helper_1i(mtthi, t0, 2);
break;
case 10:
- tcg_gen_helper_0_1i(do_mttacx, t0, 2);
+ gen_helper_1i(mttacx, t0, 2);
break;
case 12:
- tcg_gen_helper_0_1i(do_mttlo, t0, 3);
+ gen_helper_1i(mttlo, t0, 3);
break;
case 13:
- tcg_gen_helper_0_1i(do_mtthi, t0, 3);
+ gen_helper_1i(mtthi, t0, 3);
break;
case 14:
- tcg_gen_helper_0_1i(do_mttacx, t0, 3);
+ gen_helper_1i(mttacx, t0, 3);
break;
case 16:
- tcg_gen_helper_0_1(do_mttdsp, t0);
+ gen_helper_mttdsp(t0);
break;
default:
goto die;
@@ -5449,22 +5405,22 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
case 2:
/* XXX: For now we support only a single FPU context. */
if (h == 0) {
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, rd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
} else {
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(fp0, rd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- tcg_gen_helper_0_1i(do_ctc1, t0, rd);
+ gen_helper_1i(ctc1, t0, rd);
break;
/* COP2: Not implemented. */
case 4:
@@ -5504,7 +5460,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
return;
}
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
gen_store_gpr(t0, rt);
@@ -5514,7 +5470,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
break;
case OPC_MTC0:
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
save_cpu_state(ctx, 1);
@@ -5531,7 +5487,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
return;
}
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
gen_store_gpr(t0, rt);
@@ -5542,7 +5498,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
case OPC_DMTC0:
check_insn(env, ctx, ISA_MIPS3);
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
save_cpu_state(ctx, 1);
@@ -5572,31 +5528,31 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
opn = "tlbwi";
if (!env->tlb->do_tlbwi)
goto die;
- tcg_gen_helper_0_0(env->tlb->do_tlbwi);
+ gen_helper_tlbwi();
break;
case OPC_TLBWR:
opn = "tlbwr";
if (!env->tlb->do_tlbwr)
goto die;
- tcg_gen_helper_0_0(env->tlb->do_tlbwr);
+ gen_helper_tlbwr();
break;
case OPC_TLBP:
opn = "tlbp";
if (!env->tlb->do_tlbp)
goto die;
- tcg_gen_helper_0_0(env->tlb->do_tlbp);
+ gen_helper_tlbp();
break;
case OPC_TLBR:
opn = "tlbr";
if (!env->tlb->do_tlbr)
goto die;
- tcg_gen_helper_0_0(env->tlb->do_tlbr);
+ gen_helper_tlbr();
break;
case OPC_ERET:
opn = "eret";
check_insn(env, ctx, ISA_MIPS2);
save_cpu_state(ctx, 1);
- tcg_gen_helper_0_0(do_eret);
+ gen_helper_eret();
ctx->bstate = BS_EXCP;
break;
case OPC_DERET:
@@ -5607,7 +5563,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
generate_exception(ctx, EXCP_RI);
} else {
save_cpu_state(ctx, 1);
- tcg_gen_helper_0_0(do_deret);
+ gen_helper_deret();
ctx->bstate = BS_EXCP;
}
break;
@@ -5618,7 +5574,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
ctx->pc += 4;
save_cpu_state(ctx, 1);
ctx->pc -= 4;
- tcg_gen_helper_0_0(do_wait);
+ gen_helper_wait();
ctx->bstate = BS_EXCP;
break;
default:
@@ -5637,7 +5593,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
{
target_ulong btarget;
const char *opn = "cp1 cond branch";
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
+ TCGv_i32 t0 = tcg_temp_new_i32();
if (cc != 0)
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
@@ -5787,7 +5743,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
ctx->btarget = btarget;
out:
- tcg_temp_free(t0);
+ tcg_temp_free_i32(t0);
}
/* Coprocessor 1 (FPU) */
@@ -5797,16 +5753,16 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
{
const char *opn = "cp1 move";
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
switch (opc) {
case OPC_MFC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
gen_store_gpr(t0, rt);
opn = "mfc1";
@@ -5814,31 +5770,31 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
case OPC_MTC1:
gen_load_gpr(t0, rt);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, fs);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "mtc1";
break;
case OPC_CFC1:
- tcg_gen_helper_1_i(do_cfc1, t0, fs);
+ gen_helper_1i(cfc1, t0, fs);
gen_store_gpr(t0, rt);
opn = "cfc1";
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
- tcg_gen_helper_0_1i(do_ctc1, t0, fs);
+ gen_helper_1i(ctc1, t0, fs);
opn = "ctc1";
break;
case OPC_DMFC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_mov_tl(t0, fp0);
- tcg_temp_free(fp0);
+ tcg_gen_trunc_i64_tl(t0, fp0);
+ tcg_temp_free_i64(fp0);
}
gen_store_gpr(t0, rt);
opn = "dmfc1";
@@ -5846,21 +5802,21 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
case OPC_DMTC1:
gen_load_gpr(t0, rt);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_mov_tl(fp0, t0);
+ tcg_gen_extu_tl_i64(fp0, t0);
gen_store_fpr64(ctx, fp0, fs);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "dmtc1";
break;
case OPC_MFHC1:
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, fs);
tcg_gen_ext_i32_tl(t0, fp0);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
gen_store_gpr(t0, rt);
opn = "mfhc1";
@@ -5868,11 +5824,11 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
case OPC_MTHC1:
gen_load_gpr(t0, rt);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32h(fp0, fs);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "mthc1";
break;
@@ -5892,8 +5848,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
int l1 = gen_new_label();
uint32_t ccbit;
TCGCond cond;
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv_i32 r_tmp = tcg_temp_new_i32();
if (cc)
ccbit = 1 << (24 + cc);
@@ -5907,6 +5863,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
gen_load_gpr(t0, rd);
tcg_gen_andi_i32(r_tmp, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
+ tcg_temp_free_i32(r_tmp);
gen_load_gpr(t0, rs);
gen_set_label(l1);
gen_store_gpr(t0, rd);
@@ -5917,8 +5874,8 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
{
uint32_t ccbit;
int cond;
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
int l1 = gen_new_label();
if (cc)
@@ -5934,18 +5891,19 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
gen_load_fpr32(fp0, fd);
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
+ tcg_temp_free_i32(r_tmp1);
gen_load_fpr32(fp0, fs);
gen_set_label(l1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
{
uint32_t ccbit;
int cond;
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i64 fp0 = tcg_temp_local_new_i64();
int l1 = gen_new_label();
if (cc)
@@ -5961,18 +5919,19 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t
gen_load_fpr64(ctx, fp0, fd);
tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
+ tcg_temp_free_i32(r_tmp1);
gen_load_fpr64(ctx, fp0, fs);
gen_set_label(l1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
{
uint32_t ccbit1, ccbit2;
int cond;
- TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -6003,8 +5962,8 @@ static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
gen_set_label(l2);
gen_store_fpr32h(fp0, fd);
- tcg_temp_free(r_tmp1);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(r_tmp1);
+ tcg_temp_free_i32(fp0);
}
@@ -6054,204 +6013,204 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
switch (ctx->opcode & FOP(0x3f, 0x1f)) {
case FOP(0, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- tcg_gen_helper_1_2(do_float_add_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_add_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "add.s";
optype = BINOP;
break;
case FOP(1, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- tcg_gen_helper_1_2(do_float_sub_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_sub_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "sub.s";
optype = BINOP;
break;
case FOP(2, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- tcg_gen_helper_1_2(do_float_mul_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_mul_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "mul.s";
optype = BINOP;
break;
case FOP(3, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- tcg_gen_helper_1_2(do_float_div_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_div_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "div.s";
optype = BINOP;
break;
case FOP(4, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_sqrt_s, fp0, fp0);
+ gen_helper_float_sqrt_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "sqrt.s";
break;
case FOP(5, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_abs_s, fp0, fp0);
+ gen_helper_float_abs_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "abs.s";
break;
case FOP(6, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "mov.s";
break;
case FOP(7, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_chs_s, fp0, fp0);
+ gen_helper_float_chs_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "neg.s";
break;
case FOP(8, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_roundl_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_roundl_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "round.l.s";
break;
case FOP(9, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_truncl_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_truncl_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "trunc.l.s";
break;
case FOP(10, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_ceill_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_ceill_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "ceil.l.s";
break;
case FOP(11, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_floorl_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_floorl_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "floor.l.s";
break;
case FOP(12, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_roundw_s, fp0, fp0);
+ gen_helper_float_roundw_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "round.w.s";
break;
case FOP(13, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_truncw_s, fp0, fp0);
+ gen_helper_float_truncw_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "trunc.w.s";
break;
case FOP(14, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_ceilw_s, fp0, fp0);
+ gen_helper_float_ceilw_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "ceil.w.s";
break;
case FOP(15, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_floorw_s, fp0, fp0);
+ gen_helper_float_floorw_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "floor.w.s";
break;
@@ -6262,14 +6221,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(18, 16):
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
gen_load_fpr32(fp0, fs);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -6278,14 +6237,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(19, 16):
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
gen_load_fpr32(fp0, fs);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -6294,134 +6253,134 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(21, 16):
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_recip_s, fp0, fp0);
+ gen_helper_float_recip_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "recip.s";
break;
case FOP(22, 16):
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_rsqrt_s, fp0, fp0);
+ gen_helper_float_rsqrt_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "rsqrt.s";
break;
case FOP(28, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, fd);
- tcg_gen_helper_1_2(do_float_recip2_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_recip2_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "recip2.s";
break;
case FOP(29, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_recip1_s, fp0, fp0);
+ gen_helper_float_recip1_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "recip1.s";
break;
case FOP(30, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_rsqrt1_s, fp0, fp0);
+ gen_helper_float_rsqrt1_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "rsqrt1.s";
break;
case FOP(31, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
- tcg_gen_helper_1_2(do_float_rsqrt2_s, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_rsqrt2_s(fp0, fp0, fp1);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "rsqrt2.s";
break;
case FOP(33, 16):
check_cp1_registers(ctx, fd);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_cvtd_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_cvtd_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "cvt.d.s";
break;
case FOP(36, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_cvtw_s, fp0, fp0);
+ gen_helper_float_cvtw_s(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "cvt.w.s";
break;
case FOP(37, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_cvtl_s, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_cvtl_s(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "cvt.l.s";
break;
case FOP(38, 16):
check_cp1_64bitmode(ctx);
{
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i64 fp64 = tcg_temp_new_i64();
+ TCGv_i32 fp32_0 = tcg_temp_new_i32();
+ TCGv_i32 fp32_1 = tcg_temp_new_i32();
gen_load_fpr32(fp32_0, fs);
gen_load_fpr32(fp32_1, ft);
tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1);
- tcg_temp_free(fp32_1);
- tcg_temp_free(fp32_0);
+ tcg_temp_free_i32(fp32_1);
+ tcg_temp_free_i32(fp32_0);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "cvt.ps.s";
break;
@@ -6442,8 +6401,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(62, 16):
case FOP(63, 16):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
@@ -6455,22 +6414,22 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
gen_cmp_s(func-48, fp0, fp1, cc);
opn = condnames[func-48];
}
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
}
break;
case FOP(0, 17):
check_cp1_registers(ctx, fs | ft | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_add_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_add_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "add.d";
optype = BINOP;
@@ -6478,15 +6437,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(1, 17):
check_cp1_registers(ctx, fs | ft | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_sub_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_sub_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "sub.d";
optype = BINOP;
@@ -6494,15 +6453,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(2, 17):
check_cp1_registers(ctx, fs | ft | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_mul_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_mul_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "mul.d";
optype = BINOP;
@@ -6510,15 +6469,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(3, 17):
check_cp1_registers(ctx, fs | ft | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_div_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_div_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "div.d";
optype = BINOP;
@@ -6526,151 +6485,151 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(4, 17):
check_cp1_registers(ctx, fs | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_sqrt_d, fp0, fp0);
+ gen_helper_float_sqrt_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "sqrt.d";
break;
case FOP(5, 17):
check_cp1_registers(ctx, fs | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_abs_d, fp0, fp0);
+ gen_helper_float_abs_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "abs.d";
break;
case FOP(6, 17):
check_cp1_registers(ctx, fs | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "mov.d";
break;
case FOP(7, 17):
check_cp1_registers(ctx, fs | fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_chs_d, fp0, fp0);
+ gen_helper_float_chs_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "neg.d";
break;
case FOP(8, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_roundl_d, fp0, fp0);
+ gen_helper_float_roundl_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "round.l.d";
break;
case FOP(9, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_truncl_d, fp0, fp0);
+ gen_helper_float_truncl_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "trunc.l.d";
break;
case FOP(10, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_ceill_d, fp0, fp0);
+ gen_helper_float_ceill_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "ceil.l.d";
break;
case FOP(11, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_floorl_d, fp0, fp0);
+ gen_helper_float_floorl_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "floor.l.d";
break;
case FOP(12, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_roundw_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_roundw_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "round.w.d";
break;
case FOP(13, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_truncw_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_truncw_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "trunc.w.d";
break;
case FOP(14, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_ceilw_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_ceilw_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "ceil.w.d";
break;
case FOP(15, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_floorw_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_floorw_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "floor.w.d";
break;
@@ -6681,14 +6640,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(18, 17):
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i64 fp0 = tcg_temp_local_new_i64();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -6697,14 +6656,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(19, 17):
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i64 fp0 = tcg_temp_local_new_i64();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -6713,78 +6672,78 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(21, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_recip_d, fp0, fp0);
+ gen_helper_float_recip_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "recip.d";
break;
case FOP(22, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_rsqrt_d, fp0, fp0);
+ gen_helper_float_rsqrt_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "rsqrt.d";
break;
case FOP(28, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_recip2_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_recip2_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "recip2.d";
break;
case FOP(29, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_recip1_d, fp0, fp0);
+ gen_helper_float_recip1_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "recip1.d";
break;
case FOP(30, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_rsqrt1_d, fp0, fp0);
+ gen_helper_float_rsqrt1_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "rsqrt1.d";
break;
case FOP(31, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_rsqrt2_d, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_rsqrt2_d(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "rsqrt2.d";
break;
@@ -6805,8 +6764,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(62, 17):
case FOP(63, 17):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
@@ -6820,190 +6779,190 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
gen_cmp_d(func-48, fp0, fp1, cc);
opn = condnames[func-48];
}
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
}
break;
case FOP(32, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_cvts_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_cvts_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "cvt.s.d";
break;
case FOP(36, 17):
check_cp1_registers(ctx, fs);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_cvtw_d, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_cvtw_d(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "cvt.w.d";
break;
case FOP(37, 17):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_cvtl_d, fp0, fp0);
+ gen_helper_float_cvtl_d(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "cvt.l.d";
break;
case FOP(32, 20):
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_cvts_w, fp0, fp0);
+ gen_helper_float_cvts_w(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "cvt.s.w";
break;
case FOP(33, 20):
check_cp1_registers(ctx, fd);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(fp32, fs);
- tcg_gen_helper_1_1(do_float_cvtd_w, fp64, fp32);
- tcg_temp_free(fp32);
+ gen_helper_float_cvtd_w(fp64, fp32);
+ tcg_temp_free_i32(fp32);
gen_store_fpr64(ctx, fp64, fd);
- tcg_temp_free(fp64);
+ tcg_temp_free_i64(fp64);
}
opn = "cvt.d.w";
break;
case FOP(32, 21):
check_cp1_64bitmode(ctx);
{
- TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i32 fp32 = tcg_temp_new_i32();
+ TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- tcg_gen_helper_1_1(do_float_cvts_l, fp32, fp64);
- tcg_temp_free(fp64);
+ gen_helper_float_cvts_l(fp32, fp64);
+ tcg_temp_free_i64(fp64);
gen_store_fpr32(fp32, fd);
- tcg_temp_free(fp32);
+ tcg_temp_free_i32(fp32);
}
opn = "cvt.s.l";
break;
case FOP(33, 21):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_cvtd_l, fp0, fp0);
+ gen_helper_float_cvtd_l(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "cvt.d.l";
break;
case FOP(38, 20):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_cvtps_pw, fp0, fp0);
+ gen_helper_float_cvtps_pw(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "cvt.ps.pw";
break;
case FOP(0, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_add_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_add_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "add.ps";
break;
case FOP(1, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_sub_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_sub_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "sub.ps";
break;
case FOP(2, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_mul_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_mul_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "mul.ps";
break;
case FOP(5, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_abs_ps, fp0, fp0);
+ gen_helper_float_abs_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "abs.ps";
break;
case FOP(6, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "mov.ps";
break;
case FOP(7, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_chs_ps, fp0, fp0);
+ gen_helper_float_chs_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "neg.ps";
break;
@@ -7016,9 +6975,9 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
check_cp1_64bitmode(ctx);
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
+ TCGv_i32 fph0 = tcg_temp_local_new_i32();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
@@ -7026,8 +6985,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
gen_load_fpr32h(fph0, fs);
gen_store_fpr32(fp0, fd);
gen_store_fpr32h(fph0, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fph0);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fph0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -7037,9 +6996,9 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
check_cp1_64bitmode(ctx);
{
int l1 = gen_new_label();
- TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
+ TCGv_i32 fph0 = tcg_temp_local_new_i32();
gen_load_gpr(t0, ft);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
@@ -7047,8 +7006,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
gen_load_fpr32h(fph0, fs);
gen_store_fpr32(fp0, fd);
gen_store_fpr32h(fph0, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fph0);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fph0);
gen_set_label(l1);
tcg_temp_free(t0);
}
@@ -7057,180 +7016,180 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(24, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- tcg_gen_helper_1_2(do_float_addr_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_addr_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "addr.ps";
break;
case FOP(26, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- tcg_gen_helper_1_2(do_float_mulr_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_mulr_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "mulr.ps";
break;
case FOP(28, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, fd);
- tcg_gen_helper_1_2(do_float_recip2_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_recip2_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "recip2.ps";
break;
case FOP(29, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_recip1_ps, fp0, fp0);
+ gen_helper_float_recip1_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "recip1.ps";
break;
case FOP(30, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_rsqrt1_ps, fp0, fp0);
+ gen_helper_float_rsqrt1_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "rsqrt1.ps";
break;
case FOP(31, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- tcg_gen_helper_1_2(do_float_rsqrt2_ps, fp0, fp0, fp1);
- tcg_temp_free(fp1);
+ gen_helper_float_rsqrt2_ps(fp0, fp0, fp1);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "rsqrt2.ps";
break;
case FOP(32, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, fs);
- tcg_gen_helper_1_1(do_float_cvts_pu, fp0, fp0);
+ gen_helper_float_cvts_pu(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "cvt.s.pu";
break;
case FOP(36, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_helper_1_1(do_float_cvtpw_ps, fp0, fp0);
+ gen_helper_float_cvtpw_ps(fp0, fp0);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "cvt.pw.ps";
break;
case FOP(40, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_helper_1_1(do_float_cvts_pl, fp0, fp0);
+ gen_helper_float_cvts_pl(fp0, fp0);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "cvt.s.pl";
break;
case FOP(44, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_store_fpr32h(fp0, fd);
gen_store_fpr32(fp1, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
}
opn = "pll.ps";
break;
case FOP(45, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32h(fp1, ft);
gen_store_fpr32(fp1, fd);
gen_store_fpr32h(fp0, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
}
opn = "plu.ps";
break;
case FOP(46, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_store_fpr32(fp1, fd);
gen_store_fpr32h(fp0, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
}
opn = "pul.ps";
break;
case FOP(47, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32h(fp0, fs);
gen_load_fpr32h(fp1, ft);
gen_store_fpr32(fp1, fd);
gen_store_fpr32h(fp0, fd);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
}
opn = "puu.ps";
break;
@@ -7252,8 +7211,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
case FOP(63, 22):
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
@@ -7264,8 +7223,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
gen_cmp_ps(func-48, fp0, fp1, cc);
opn = condnames[func-48];
}
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
}
break;
default:
@@ -7292,8 +7251,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
{
const char *opn = "extended float load/store";
int store = 0;
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
if (base == 0) {
gen_load_gpr(t0, index);
@@ -7310,11 +7269,12 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
case OPC_LWXC1:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
+ tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
+ tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i32(fp0);
}
opn = "lwxc1";
break;
@@ -7322,11 +7282,11 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fd);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "ldxc1";
break;
@@ -7334,22 +7294,23 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
check_cp1_64bitmode(ctx);
tcg_gen_andi_tl(t0, t0, ~0x7);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
gen_store_fpr64(ctx, fp0, fd);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "luxc1";
break;
case OPC_SWXC1:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
- tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
- tcg_temp_free(fp0);
+ tcg_gen_extu_i32_tl(t1, fp0);
+ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
+ tcg_temp_free_i32(fp0);
}
opn = "swxc1";
store = 1;
@@ -7358,11 +7319,11 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fs);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "sdxc1";
store = 1;
@@ -7371,11 +7332,11 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
check_cp1_64bitmode(ctx);
tcg_gen_andi_tl(t0, t0, ~0x7);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
- tcg_temp_free(fp0);
+ tcg_temp_free_i64(fp0);
}
opn = "suxc1";
store = 1;
@@ -7402,11 +7363,11 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
case OPC_ALNV_PS:
check_cp1_64bitmode(ctx);
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv fph1 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv_i32 fp0 = tcg_temp_local_new_i32();
+ TCGv_i32 fph0 = tcg_temp_local_new_i32();
+ TCGv_i32 fp1 = tcg_temp_local_new_i32();
+ TCGv_i32 fph1 = tcg_temp_local_new_i32();
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -7432,28 +7393,28 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
gen_store_fpr32h(fp1, fd);
#endif
gen_set_label(l2);
- tcg_temp_free(fp0);
- tcg_temp_free(fph0);
- tcg_temp_free(fp1);
- tcg_temp_free(fph1);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fph0);
+ tcg_temp_free_i32(fp1);
+ tcg_temp_free_i32(fph1);
}
opn = "alnv.ps";
break;
case OPC_MADD_S:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
+ TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- tcg_gen_helper_1_3(do_float_muladd_s, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_muladd_s(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i32(fp2);
}
opn = "madd.s";
break;
@@ -7461,54 +7422,54 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fd | fs | ft | fr);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_muladd_d, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_muladd_d(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "madd.d";
break;
case OPC_MADD_PS:
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_muladd_ps, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "madd.ps";
break;
case OPC_MSUB_S:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
+ TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- tcg_gen_helper_1_3(do_float_mulsub_s, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i32(fp2);
}
opn = "msub.s";
break;
@@ -7516,54 +7477,54 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fd | fs | ft | fr);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_mulsub_d, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "msub.d";
break;
case OPC_MSUB_PS:
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_mulsub_ps, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "msub.ps";
break;
case OPC_NMADD_S:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
+ TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- tcg_gen_helper_1_3(do_float_nmuladd_s, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i32(fp2);
}
opn = "nmadd.s";
break;
@@ -7571,54 +7532,54 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fd | fs | ft | fr);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_nmuladd_d, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "nmadd.d";
break;
case OPC_NMADD_PS:
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_nmuladd_ps, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "nmadd.ps";
break;
case OPC_NMSUB_S:
check_cop1x(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv_i32 fp1 = tcg_temp_new_i32();
+ TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, ft);
gen_load_fpr32(fp2, fr);
- tcg_gen_helper_1_3(do_float_nmulsub_s, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i32(fp0);
+ tcg_temp_free_i32(fp1);
gen_store_fpr32(fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i32(fp2);
}
opn = "nmsub.s";
break;
@@ -7626,36 +7587,36 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
check_cop1x(ctx);
check_cp1_registers(ctx, fd | fs | ft | fr);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_nmulsub_d, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "nmsub.d";
break;
case OPC_NMSUB_PS:
check_cp1_64bitmode(ctx);
{
- TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
- TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
+ TCGv_i64 fp0 = tcg_temp_new_i64();
+ TCGv_i64 fp1 = tcg_temp_new_i64();
+ TCGv_i64 fp2 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- tcg_gen_helper_1_3(do_float_nmulsub_ps, fp2, fp0, fp1, fp2);
- tcg_temp_free(fp0);
- tcg_temp_free(fp1);
+ gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2);
+ tcg_temp_free_i64(fp0);
+ tcg_temp_free_i64(fp1);
gen_store_fpr64(ctx, fp2, fd);
- tcg_temp_free(fp2);
+ tcg_temp_free_i64(fp2);
}
opn = "nmsub.ps";
break;
@@ -7699,11 +7660,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
{
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+ TCGv_i32 r_tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(r_tmp, ctx->hflags & ~MIPS_HFLAG_BMASK);
tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
- tcg_temp_free(r_tmp);
+ tcg_temp_free_i32(r_tmp);
}
gen_goto_tb(ctx, 1, ctx->pc + 4);
gen_set_label(l1);
@@ -7758,7 +7719,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
MIPS_INVAL("PMON / selsl");
generate_exception(ctx, EXCP_RI);
#else
- tcg_gen_helper_0_i(do_pmon, sa);
+ gen_helper_0i(pmon, sa);
#endif
break;
case OPC_SYSCALL:
@@ -7878,24 +7839,24 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_RDHWR:
check_insn(env, ctx, ISA_MIPS32R2);
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_rdhwr_cpunum, t0);
+ gen_helper_rdhwr_cpunum(t0);
break;
case 1:
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_rdhwr_synci_step, t0);
+ gen_helper_rdhwr_synci_step(t0);
break;
case 2:
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_rdhwr_cc, t0);
+ gen_helper_rdhwr_cc(t0);
break;
case 3:
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
+ gen_helper_rdhwr_ccres(t0);
break;
case 29:
if (env->user_mode_only) {
@@ -7917,12 +7878,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_FORK:
check_insn(env, ctx, ASE_MT);
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
- TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
+ TCGv t1 = tcg_temp_local_new();
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- tcg_gen_helper_0_2(do_fork, t0, t1);
+ gen_helper_fork(t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@@ -7930,10 +7891,10 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_YIELD:
check_insn(env, ctx, ASE_MT);
{
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
gen_load_gpr(t0, rs);
- tcg_gen_helper_1_1(do_yield, t0, t0);
+ gen_helper_yield(t0, t0);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
}
@@ -8005,37 +7966,37 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_MFMC0:
#ifndef CONFIG_USER_ONLY
if (!env->user_mode_only) {
- TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv t0 = tcg_temp_local_new();
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_1(do_dmt, t0, t0);
+ gen_helper_dmt(t0, t0);
break;
case OPC_EMT:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_1(do_emt, t0, t0);
+ gen_helper_emt(t0, t0);
break;
case OPC_DVPE:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_1(do_dvpe, t0, t0);
+ gen_helper_dvpe(t0, t0);
break;
case OPC_EVPE:
check_insn(env, ctx, ASE_MT);
- tcg_gen_helper_1_1(do_evpe, t0, t0);
+ gen_helper_evpe(t0, t0);
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_di, t0);
+ gen_helper_di(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
save_cpu_state(ctx, 1);
- tcg_gen_helper_1_0(do_ei, t0);
+ gen_helper_ei(t0);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
@@ -8329,7 +8290,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
if (env->breakpoints[j] == ctx.pc) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
- tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
+ gen_helper_0i(raise_exception, EXCP_DEBUG);
/* Include the breakpoint location or the tb won't
* be flushed when it must be. */
ctx.pc += 4;
@@ -8376,11 +8337,11 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
gen_io_end();
if (env->singlestep_enabled) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
- tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
+ gen_helper_0i(raise_exception, EXCP_DEBUG);
} else {
switch (ctx.bstate) {
case BS_STOP:
- tcg_gen_helper_0_0(do_interrupt_restart);
+ gen_helper_interrupt_restart();
gen_goto_tb(&ctx, 0, ctx.pc);
break;
case BS_NONE:
@@ -8388,7 +8349,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
gen_goto_tb(&ctx, 0, ctx.pc);
break;
case BS_EXCP:
- tcg_gen_helper_0_0(do_interrupt_restart);
+ gen_helper_interrupt_restart();
tcg_gen_exit_tb(0);
break;
case BS_BRANCH:
@@ -8540,53 +8501,52 @@ static void mips_tcg_init(void)
if (inited)
return;
- cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
for (i = 0; i < 32; i++)
- cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.gpr[i]),
regnames[i]);
- cpu_PC = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_PC = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
- cpu_HI[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.HI[i]),
regnames_HI[i]);
- cpu_LO[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.LO[i]),
regnames_LO[i]);
- cpu_ACX[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.ACX[i]),
regnames_ACX[i]);
}
- cpu_dspctrl = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.DSPControl),
"DSPControl");
- bcond = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, bcond), "bcond");
- btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ bcond = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, bcond), "bcond");
+ btarget = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, btarget), "btarget");
for (i = 0; i < 32; i++)
- fpu_fpr32[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),
- fregnames[i]);
+ fpu_fpr32[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),
+ fregnames[i]);
for (i = 0; i < 32; i++)
- fpu_fpr64[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, active_fpu.fpr[i]),
- fregnames_64[i]);
+ fpu_fpr64[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i]),
+ fregnames_64[i]);
for (i = 0; i < 32; i++)
- fpu_fpr32h[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]),
- fregnames_h[i]);
- fpu_fcr0 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr0),
- "fcr0");
- fpu_fcr31 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr31),
- "fcr31");
+ fpu_fpr32h[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]),
+ fregnames_h[i]);
+ fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, active_fpu.fcr0),
+ "fcr0");
+ fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, active_fpu.fcr31),
+ "fcr31");
/* register helpers */
-#undef DEF_HELPER
-#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
+#define GEN_HELPER 2
#include "helper.h"
inited = 1;
generated by cgit v1.1 at 2024-12-24 01:34:31 +0000