Actually enable 64bit configuration.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2565 c046a42c-6fe2-441c-8c8c-71466251a162

8 files changed, 35 insertions, 38 deletions

diff --git a/target-mips/exec.h b/target-mips/exec.h
index 6b32027..54f4d5a 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -65,7 +65,7 @@ static inline void regs_to_env(void)
 {
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 #if TARGET_LONG_BITS > HOST_LONG_BITS
 void do_dsll (void);
 void do_dsll32 (void);
@@ -92,7 +92,7 @@ void do_msubu (void);
 void do_ddiv (void);
 void do_ddivu (void);
 #endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void do_dmult (void);
 void do_dmultu (void);
 #endif
@@ -114,7 +114,7 @@ void do_lwl_raw (uint32_t);
 void do_lwr_raw (uint32_t);
 uint32_t do_swl_raw (uint32_t);
 uint32_t do_swr_raw (uint32_t);
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void do_ldl_raw (uint64_t);
 void do_ldr_raw (uint64_t);
 uint64_t do_sdl_raw (uint64_t);
@@ -129,7 +129,7 @@ uint32_t do_swl_user (uint32_t);
 uint32_t do_swl_kernel (uint32_t);
 uint32_t do_swr_user (uint32_t);
 uint32_t do_swr_kernel (uint32_t);
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void do_ldl_user (uint64_t);
 void do_ldl_kernel (uint64_t);
 void do_ldr_user (uint64_t);
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index b59af0f..8b29e8b 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -6,9 +6,6 @@
 /* If we want to use host float regs... */
 //#define USE_HOST_FLOAT_REGS
 
-/* 32 bits target */
-#undef MIPS_HAS_MIPS64
-//#define MIPS_HAS_MIPS64 1
 /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12
 /* Uses MIPS R4Kc TLB model */
@@ -16,7 +13,7 @@
 #define MIPS_TLB_NB 16
 #define MIPS_TLB_MAX 128
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 #define TARGET_LONG_BITS 64
 #else
 #define TARGET_LONG_BITS 32
diff --git a/target-mips/op.c b/target-mips/op.c
index fecf18c..db430a7 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -386,7 +386,7 @@ void op_divu (void)
     RETURN();
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 /* Arithmetic */
 void op_dadd (void)
 {
@@ -464,7 +464,7 @@ void op_ddivu (void)
     RETURN();
 }
 #endif
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
 
 /* Logical */
 void op_and (void)
@@ -586,7 +586,7 @@ void op_clz (void)
     RETURN();
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 
 #if TARGET_LONG_BITS > HOST_LONG_BITS
 /* Those might call libgcc functions.  */
@@ -891,7 +891,7 @@ void op_msubu (void)
 }
 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void op_dmult (void)
 {
     CALL_FROM_TB0(do_dmult);
@@ -2213,7 +2213,7 @@ void op_wsbh(void)
     RETURN();
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void op_dext(void)
 {
     unsigned int pos = PARAM1;
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index fb70f51..af39387 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -79,7 +79,7 @@ void do_raise_exception_direct (uint32_t exception)
 #undef MEMSUFFIX
 #endif
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 #if TARGET_LONG_BITS > HOST_LONG_BITS
 /* Those might call libgcc functions.  */
 void do_dsll (void)
@@ -161,7 +161,7 @@ void do_drotrv (void)
        T0 = T1;
 }
 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
 
 /* 64 bits arithmetic for 32 bits hosts */
 #if TARGET_LONG_BITS > HOST_LONG_BITS
@@ -219,7 +219,7 @@ void do_msubu (void)
 }
 #endif
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void do_dmult (void)
 {
     /* XXX */
diff --git a/target-mips/op_helper_mem.c b/target-mips/op_helper_mem.c
index e0030e0..56eeaad 100644
--- a/target-mips/op_helper_mem.c
+++ b/target-mips/op_helper_mem.c
@@ -124,7 +124,7 @@ uint32_t glue(do_swr, MEMSUFFIX) (uint32_t tmp)
     return tmp;
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 
 # ifdef TARGET_WORDS_BIGENDIAN
 #define GET_LMASK64(v) ((v) & 4)
@@ -298,4 +298,4 @@ uint64_t glue(do_sdr, MEMSUFFIX) (uint64_t tmp)
     return tmp;
 }
 
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
diff --git a/target-mips/op_mem.c b/target-mips/op_mem.c
index 823cfe8..a199172 100644
--- a/target-mips/op_mem.c
+++ b/target-mips/op_mem.c
@@ -126,7 +126,7 @@ void glue(op_sc, MEMSUFFIX) (void)
     RETURN();
 }
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 void glue(op_ld, MEMSUFFIX) (void)
 {
     T0 = glue(ldq, MEMSUFFIX)(T0);
@@ -190,7 +190,7 @@ void glue(op_scd, MEMSUFFIX) (void)
     }
     RETURN();
 }
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
 
 void glue(op_lwc1, MEMSUFFIX) (void)
 {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6582108..469f2ec 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -611,7 +611,7 @@ static GenOpFunc *gen_op_s##width[] = {                                       \
 }
 #endif
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 OP_LD_TABLE(d);
 OP_LD_TABLE(dl);
 OP_LD_TABLE(dr);
@@ -660,7 +660,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
      * memory access
      */
     switch (opc) {
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_LD:
         op_ldst(ld);
         GEN_STORE_TN_REG(rt, T0);
@@ -872,7 +872,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
         gen_op_add();
         opn = "addiu";
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DADDI:
         save_cpu_state(ctx, 1);
         gen_op_daddo();
@@ -923,7 +923,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
             opn = "srl";
        }
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DSLL:
         gen_op_dsll();
         opn = "dsll";
@@ -1003,7 +1003,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
         gen_op_sub();
         opn = "subu";
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DADD:
         save_cpu_state(ctx, 1);
         gen_op_daddo();
@@ -1076,7 +1076,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
             opn = "srlv";
        }
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DSLLV:
         gen_op_dsllv();
         opn = "dsllv";
@@ -1168,7 +1168,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
         gen_op_multu();
         opn = "multu";
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DDIV:
         gen_op_ddiv();
         opn = "ddiv";
@@ -1229,7 +1229,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
         gen_op_clz();
         opn = "clz";
         break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     case OPC_DCLO:
         gen_op_dclo();
         opn = "dclo";
@@ -4538,7 +4538,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
 /* MIPS16 extension to MIPS32 */
 /* SmartMIPS extension to MIPS32 */
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
 /* Coprocessor 3 (FPU) */
 
 /* MDMX extension to MIPS64 */
@@ -4643,7 +4643,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             }
             break;
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
        /* MIPS64 specific opcodes */
         case OPC_DSLL:
         case OPC_DSRL ... OPC_DSRA:
@@ -4690,7 +4690,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             }
             /* Treat as a noop */
             break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
         case OPC_DCLZ ... OPC_DCLO:
             gen_cl(ctx, op1, rd, rs);
             break;
@@ -4757,7 +4757,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
            }
            GEN_STORE_TN_REG(rt, T0);
            break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
        case OPC_DEXTM ... OPC_DEXT:
        case OPC_DINSM ... OPC_DINS:
            gen_bitops(ctx, op1, rt, rs, sa, rd);
@@ -4812,7 +4812,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
         switch (op1) {
         case OPC_MFC0:
         case OPC_MTC0:
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
         case OPC_DMFC0:
         case OPC_DMTC0:
 #endif
@@ -4898,7 +4898,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             case OPC_CFC1:
             case OPC_MTC1:
             case OPC_CTC1:
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
             case OPC_DMFC1:
             case OPC_DMTC1:
 #endif
@@ -4948,7 +4948,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
         }
         break;
 
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
     /* MIPS64 opcodes */
     case OPC_LWU:
     case OPC_LDL ... OPC_LDR:
@@ -5197,7 +5197,7 @@ void dump_fpu (CPUState *env)
     }
 }
 
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
 /* Debug help: The architecture requires 32bit code to maintain proper
    sign-extened values on 64bit machines.  */
 
@@ -5255,7 +5255,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
                 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
     if (c0_status & (1 << CP0St_CU1))
         fpu_dump_state(env, f, cpu_fprintf, flags);
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
     cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
 #endif
 }
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 6aacfb7..456a6cd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -74,7 +74,7 @@ struct mips_def_t {
 /* MIPS CPU definitions */
 static mips_def_t mips_defs[] =
 {
-#ifndef MIPS_HAS_MIPS64
+#ifndef TARGET_MIPS64
     {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,