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| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-01 20:01:19 +0000 |
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| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-01 20:01:19 +0000 |
| commit | 9656f324d25895ec16ebc5eaf624e28a96c1f1be (patch) | |
| tree | 493d25a4b894fea24ee91d07efea4309044ba54c /target-mips | |
| parent | a5cdf952204931960bbb269494469843be789b52 (diff) | |
| download | qemu-9656f324d25895ec16ebc5eaf624e28a96c1f1be.zip qemu-9656f324d25895ec16ebc5eaf624e28a96c1f1be.tar.gz qemu-9656f324d25895ec16ebc5eaf624e28a96c1f1be.tar.bz2 | |
Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/cpu.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 93c1610..e747bc8 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -411,9 +411,7 @@ struct CPUMIPSState { /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; /* Qemu */ - int interrupt_request; int error_code; - int user_mode_only; /* user mode only simulation */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x01FF |