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| author | Eric Johnson <ericj@mips.com> | 2011-09-17 17:28:16 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-08-27 22:18:02 +0200 |
| commit | 36c6711bbe79642b0102416a9dd4243505e874a6 (patch) | |
| tree | 876569a96c40c06be0c5cf2140608a49fbb7db9b /target-mips | |
| parent | 2e15497c5b8d0d172dece0cf56e2d2e977a6b679 (diff) | |
| download | qemu-36c6711bbe79642b0102416a9dd4243505e874a6.zip qemu-36c6711bbe79642b0102416a9dd4243505e874a6.tar.gz qemu-36c6711bbe79642b0102416a9dd4243505e874a6.tar.bz2 | |
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This
is required for AVPs to pass.
Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 0cff905..b293419 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10031,7 +10031,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, const char *opn = "ldst_pair"; TCGv t0, t1; - if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) { + if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { generate_exception(ctx, EXCP_RI); return; } @@ -10043,6 +10043,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, switch (opc) { case LWP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); @@ -10064,6 +10068,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, break; #ifdef TARGET_MIPS64 case LDP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_ld(t1, t0, ctx); gen_store_gpr(t1, rd); |