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| author | Stefan Weil <weil@mail.berlios.de> | 2009-12-15 14:03:03 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-12-17 00:28:58 +0100 |
| commit | ab3aee26c480eb5e522896b3f758a3c3c3c9f9c6 (patch) | |
| tree | 36e91992e18116c1fe22fd9dd7e19280e1e8cba1 /target-mips/translate_init.c | |
| parent | 212df029754caabba45f941fbd22ec219b934ef9 (diff) | |
| download | qemu-ab3aee26c480eb5e522896b3f758a3c3c3c9f9c6.zip qemu-ab3aee26c480eb5e522896b3f758a3c3c3c9f9c6.tar.gz qemu-ab3aee26c480eb5e522896b3f758a3c3c3c9f9c6.tar.bz2 | |
target-mips: No MIPS16 support for 4Kc, 4KEc cores
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487.
4Kc and 4KEc don't support MIPS16.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index dc14be5..b79ed56 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -105,7 +105,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .CP0_LLAddr_rw_bitmask = 0, @@ -147,7 +147,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .CP0_LLAddr_rw_bitmask = 0, @@ -188,7 +188,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, |