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| author | Jia Liu <proljc@gmail.com> | 2012-10-24 22:17:02 +0800 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-10-31 20:24:06 +0100 |
| commit | 853c3240c0753735b82fe80a86123e09234f5448 (patch) | |
| tree | 30743eba7a8bdf30a60e46bc8e44c8ab3ef74a10 /target-mips/translate.c | |
| parent | 235eb0158cfb31bb8a7cad7296e2327d7f7349fc (diff) | |
| download | qemu-853c3240c0753735b82fe80a86123e09234f5448.zip qemu-853c3240c0753735b82fe80a86123e09234f5448.tar.gz qemu-853c3240c0753735b82fe80a86123e09234f5448.tar.bz2 | |
target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index ed55e26..586f564 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -948,6 +948,24 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) generate_exception(ctx, EXCP_RI); } +/* Verify that the processor is running with DSP instructions enabled. + This is enabled by CP0 Status register MX(24) bit. + */ + +static inline void check_dsp(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + +static inline void check_dspr2(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags) @@ -13209,6 +13227,11 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->CP0_Status |= (1 << CP0St_CU1); } + if (env->cpu_model->insn_flags & ASE_DSPR2) { + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } else if (env->cpu_model->insn_flags & ASE_DSP) { + env->hflags |= MIPS_HFLAG_DSP; + } #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, |