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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-09 09:33:33 +0000 |
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| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-09 09:33:33 +0000 |
| commit | a6763a588127d8b0f7e64312e9153c6c6bae822f (patch) | |
| tree | bca17b21adf269ef2552351f9b4af2f3dd7cd6b6 /target-mips/op.c | |
| parent | 204a1b8d5ec12af7f0e4757f51802672fc2e6681 (diff) | |
| download | qemu-a6763a588127d8b0f7e64312e9153c6c6bae822f.zip qemu-a6763a588127d8b0f7e64312e9153c6c6bae822f.tar.gz qemu-a6763a588127d8b0f7e64312e9153c6c6bae822f.tar.bz2 | |
Fix MIPS64 address computation specialcase, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op.c')
| -rw-r--r-- | target-mips/op.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index aedd7bd..9b0cee0 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -289,6 +289,22 @@ void op_store_LO (void) #undef MEMSUFFIX #endif +/* Addresses computation */ +void op_addr_add (void) +{ +/* For compatibility with 32-bit code, data reference in user mode + with Status_UX = 0 should be casted to 32-bit and sign extended. + See the MIPS64 PRA manual, section 4.10. */ +#ifdef TARGET_MIPS64 + if ((env->CP0_Status & (1 << CP0St_UM)) && + !(env->CP0_Status & (1 << CP0St_UX))) + T0 = (int64_t)(int32_t)(T0 + T1); + else +#endif + T0 += T1; + RETURN(); +} + /* Arithmetic */ void op_add (void) { |