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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 18:05:37 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-08 18:05:37 +0000 |
| commit | d26bc2118e99702eb8c1bb240786bcadd7fa21ac (patch) | |
| tree | 2d3523234b61325aff6bf5eb857a67a5fddaeb97 /target-mips/op.c | |
| parent | 5850586c072456e6f007096ea8a489c97118f8f1 (diff) | |
| download | qemu-d26bc2118e99702eb8c1bb240786bcadd7fa21ac.zip qemu-d26bc2118e99702eb8c1bb240786bcadd7fa21ac.tar.gz qemu-d26bc2118e99702eb8c1bb240786bcadd7fa21ac.tar.bz2 | |
Clean out the N32 macros from target-mips, and introduce MIPS ABI specific
defines for linux-user.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op.c')
| -rw-r--r-- | target-mips/op.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index 569c2f2..f5796c8 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -301,7 +301,7 @@ void op_addr_add (void) /* For compatibility with 32-bit code, data reference in user mode with Status_UX = 0 should be casted to 32-bit and sign extended. See the MIPS64 PRA manual, section 4.10. */ -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) T0 = (int64_t)(int32_t)(T0 + T1); @@ -384,7 +384,7 @@ void op_divu (void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) /* Arithmetic */ void op_dadd (void) { @@ -453,7 +453,7 @@ void op_ddivu (void) RETURN(); } #endif -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ +#endif /* TARGET_MIPS64 */ /* Logical */ void op_and (void) @@ -552,7 +552,7 @@ void op_clz (void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) #if TARGET_LONG_BITS > HOST_LONG_BITS /* Those might call libgcc functions. */ @@ -743,7 +743,7 @@ void op_dclz (void) RETURN(); } #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ +#endif /* TARGET_MIPS64 */ /* 64 bits arithmetic */ #if TARGET_LONG_BITS > HOST_LONG_BITS @@ -846,7 +846,7 @@ void op_msubu (void) } #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) void op_dmult (void) { CALL_FROM_TB4(muls64, &(env->LO[0][env->current_tc]), &(env->HI[0][env->current_tc]), T0, T1); @@ -950,7 +950,7 @@ void op_save_btarget (void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) void op_save_btarget64 (void) { env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2; @@ -1784,7 +1784,7 @@ void op_mtc0_entryhi (void) /* 1k pages not implemented */ val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) val &= env->SEGMask; #endif old = env->CP0_EntryHi; @@ -2011,7 +2011,7 @@ void op_mtc0_desave (void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) void op_dmfc0_yqmask (void) { T0 = env->CP0_YQMask; @@ -2125,7 +2125,7 @@ void op_dmfc0_errorepc (void) T0 = env->CP0_ErrorEPC; RETURN(); } -#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ +#endif /* TARGET_MIPS64 */ /* MIPS MT functions */ void op_mftgpr(void) @@ -3039,7 +3039,7 @@ void op_save_pc (void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) void op_save_pc64 (void) { env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2; @@ -3111,7 +3111,7 @@ void op_wsbh(void) RETURN(); } -#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) void op_dext(void) { unsigned int pos = PARAM1; |