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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2006-12-06 17:42:40 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2006-12-06 17:42:40 +0000
commit814b9a47490c4500fd105b524b8354764e6655e5 (patch)
tree77b03656e085fd47513316bc1b4ea6969e1e0fb2 /target-mips/cpu.h
parentec2309289d39dcdfd1a766b945b46d8a0e0be3a4 (diff)
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MIPS TLB performance improvements, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2220 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 330f9eb..3ade7bc 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -94,7 +94,8 @@ struct CPUMIPSState {
#endif
#if defined(MIPS_USES_R4K_TLB)
- tlb_t tlb[MIPS_TLB_NB];
+ tlb_t tlb[MIPS_TLB_MAX];
+ uint32_t tlb_in_use;
#endif
uint32_t CP0_index;
uint32_t CP0_random;