diff options
author | Andreas Färber <afaerber@suse.de> | 2012-12-17 06:18:02 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2013-01-15 04:09:13 +0100 |
commit | 55e5c2850293547203874098f7cec148ffd12dfa (patch) | |
tree | f9a9cc316999b7b52726b5186a925022b3747daa /target-mips/cpu.c | |
parent | 1b1ed8dc40635d60dd95c04658989af63542fcbf (diff) | |
download | qemu-55e5c2850293547203874098f7cec148ffd12dfa.zip qemu-55e5c2850293547203874098f7cec148ffd12dfa.tar.gz qemu-55e5c2850293547203874098f7cec148ffd12dfa.tar.bz2 |
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset().
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/cpu.c')
-rw-r--r-- | target-mips/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 0044062..10ff46d 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -29,8 +29,16 @@ static void mips_cpu_reset(CPUState *s) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); + log_cpu_state(env, 0); + } + mcc->parent_reset(s); + memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + tlb_flush(env, 1); + cpu_state_reset(env); } |