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| author | Andreas Färber <afaerber@suse.de> | 2013-06-28 23:18:47 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-26 23:23:54 +0200 |
| commit | a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 (patch) | |
| tree | 0a87f5f9ab3ff51ef996c69ded7cfa8f97768e92 /target-mips/cpu.c | |
| parent | 19a77215f1ba966c4d37dadec45f38be789b8529 (diff) | |
| download | qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.zip qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.gz qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.bz2 | |
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips/cpu.c')
| -rw-r--r-- | target-mips/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 4834c86..e667fb7 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -104,6 +104,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->do_unassigned_access = mips_cpu_unassigned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; #endif + + cc->gdb_num_core_regs = 73; } static const TypeInfo mips_cpu_type_info = { |