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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-04-23 14:27:09 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-04-26 11:28:50 +0200 |
| commit | a1bff71c56f2d1048244c829b63797940dd4ba0e (patch) | |
| tree | 3a6575ef6d40aea660569af5dab8905122e3b9a6 /target-microblaze | |
| parent | e3351000cd682200835763caca87adf708ed1c65 (diff) | |
| download | qemu-a1bff71c56f2d1048244c829b63797940dd4ba0e.zip qemu-a1bff71c56f2d1048244c829b63797940dd4ba0e.tar.gz qemu-a1bff71c56f2d1048244c829b63797940dd4ba0e.tar.bz2 | |
microblaze: Add internal base vectors reg
Configurable at CPU synthesis/instantiation.
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-microblaze')
| -rw-r--r-- | target-microblaze/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-microblaze/cpu.c | 8 | ||||
| -rw-r--r-- | target-microblaze/helper.c | 8 |
3 files changed, 13 insertions, 4 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index aa51cf6..ce92a4e 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -56,6 +56,7 @@ typedef struct MicroBlazeCPUClass { typedef struct MicroBlazeCPU { /*< private >*/ CPUState parent_obj; + uint32_t base_vectors; /*< public >*/ CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0f4293d..404f82c 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "qemu-common.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -119,6 +120,11 @@ static const VMStateDescription vmstate_mb_cpu = { .unmigratable = 1, }; +static Property mb_properties[] = { + DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void mb_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -133,6 +139,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = mb_cpu_do_interrupt; dc->vmsd = &vmstate_mb_cpu; + + dc->props = mb_properties; } static const TypeInfo mb_cpu_type_info = { diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index a0416d0..0dd669d 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = 0x20; + env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; case EXCP_MMU: @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, env, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = 0x20; + env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; case EXCP_IRQ: @@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = 0x10; + env->sregs[SR_PC] = cpu->base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, env, 0); break; @@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (env->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = 0x18; + env->sregs[SR_PC] = cpu->base_vectors + 0x18; } else env->sregs[SR_PC] = env->btarget; break; |