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| author | Emilio G. Cota <cota@braap.org> | 2016-06-27 15:02:01 -0400 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-10-26 08:29:01 -0700 |
| commit | 8eb8c7385608b99bed6055a22d897ff727a6cb8e (patch) | |
| tree | 059c95caf491c7c72ceb0e69fe55bf950d6a1a17 /target-i386 | |
| parent | 2a5fe8ae145ef7a3ab480922116d27efcc97b85d (diff) | |
| download | qemu-8eb8c7385608b99bed6055a22d897ff727a6cb8e.zip qemu-8eb8c7385608b99bed6055a22d897ff727a6cb8e.tar.gz qemu-8eb8c7385608b99bed6055a22d897ff727a6cb8e.tar.bz2 | |
target-i386: emulate LOCK'ed NEG using cmpxchg helper
[rth: Move redundant qemu_load out of cmpxchg loop.]
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <1467054136-10430-16-git-send-email-cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/translate.c | 38 |
1 files changed, 34 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 6d71564..d2edbd9 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4712,11 +4712,41 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; case 3: /* neg */ - tcg_gen_neg_tl(cpu_T0, cpu_T0); - if (mod != 3) { - gen_op_st_v(s, ot, cpu_T0, cpu_A0); + if (s->prefix & PREFIX_LOCK) { + TCGLabel *label1; + TCGv a0, t0, t1, t2; + + if (mod == 3) { + goto illegal_op; + } + a0 = tcg_temp_local_new(); + t0 = tcg_temp_local_new(); + label1 = gen_new_label(); + + tcg_gen_mov_tl(a0, cpu_A0); + tcg_gen_mov_tl(t0, cpu_T0); + + gen_set_label(label1); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + tcg_gen_mov_tl(t2, t0); + tcg_gen_neg_tl(t1, t0); + tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1, + s->mem_index, ot | MO_LE); + tcg_temp_free(t1); + tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1); + + tcg_temp_free(t2); + tcg_temp_free(a0); + tcg_gen_mov_tl(cpu_T0, t0); + tcg_temp_free(t0); } else { - gen_op_mov_reg_v(ot, rm, cpu_T0); + tcg_gen_neg_tl(cpu_T0, cpu_T0); + if (mod != 3) { + gen_op_st_v(s, ot, cpu_T0, cpu_A0); + } else { + gen_op_mov_reg_v(ot, rm, cpu_T0); + } } gen_op_update_neg_cc(); set_cc_op(s, CC_OP_SUBB + ot); |