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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-25 21:01:05 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-25 21:01:05 +0000 |
| commit | 2a449d14922cdd65ba4bf566ad114e37e61c89e1 (patch) | |
| tree | f97ba7bd44bbdc6ddbd7a194476ff23abaf696b6 /target-i386 | |
| parent | 90426a4e2d1994026a3ca6fdc149f55730aa2b8a (diff) | |
| download | qemu-2a449d14922cdd65ba4bf566ad114e37e61c89e1.zip qemu-2a449d14922cdd65ba4bf566ad114e37e61c89e1.tar.gz qemu-2a449d14922cdd65ba4bf566ad114e37e61c89e1.tar.bz2 | |
fixed x86_64 regression
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4586 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 54fe679..bba9b56 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1511,15 +1511,15 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, if (is_right) { if (is_arith) { gen_exts(ot, cpu_T[0]); - tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); } else { gen_extu(ot, cpu_T[0]); - tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); } } else { - tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1); + tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); } } @@ -1532,7 +1532,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, /* update eflags if non zero shift */ if (op2 != 0) { - tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0); + tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); if (is_right) s->cc_op = CC_OP_SARB + ot; |