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| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-03-31 12:58:30 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-04-13 13:51:56 +0200 |
| commit | e71827bc0ed50edb31bee6050bc96b3bd1e0c055 (patch) | |
| tree | b2dcf9af2e14a42a87e9c09a6a02a0f2cc29f773 /target-i386 | |
| parent | 8dbd3fc37593c81a04a62cb4266ba9127de4498a (diff) | |
| download | qemu-e71827bc0ed50edb31bee6050bc96b3bd1e0c055.zip qemu-e71827bc0ed50edb31bee6050bc96b3bd1e0c055.tar.gz qemu-e71827bc0ed50edb31bee6050bc96b3bd1e0c055.tar.bz2 | |
target-i386: add pclmulqdq instruction
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.c | 19 | ||||
| -rw-r--r-- | target-i386/ops_sse.h | 24 | ||||
| -rw-r--r-- | target-i386/ops_sse_header.h | 5 | ||||
| -rw-r--r-- | target-i386/translate.c | 3 |
4 files changed, 41 insertions, 10 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 356378c..f334b54 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -387,17 +387,16 @@ typedef struct x86_def_t { CPUID_PSE36 (needed for Solaris) */ /* missing: CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ -#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ - CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | \ - CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | \ - CPUID_EXT_HYPERVISOR) +#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ + CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ + CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ + CPUID_EXT_MOVBE | CPUID_EXT_HYPERVISOR) /* missing: - CPUID_EXT_PCLMULQDQ, CPUID_EXT_DTES64, CPUID_EXT_DSCPL, - CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, - CPUID_EXT_CID, CPUID_EXT_FMA, CPUID_EXT_XTPR, CPUID_EXT_PDCM, - CPUID_EXT_PCID, CPUID_EXT_DCA, CPUID_EXT_X2APIC, - CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, CPUID_EXT_XSAVE, - CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C, + CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, + CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, + CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, + CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, + CPUID_EXT_XSAVE, CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C, CPUID_EXT_RDRAND */ #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h index a11dba1..2ee5b8d 100644 --- a/target-i386/ops_sse.h +++ b/target-i386/ops_sse.h @@ -2179,6 +2179,30 @@ target_ulong helper_popcnt(CPUX86State *env, target_ulong n, uint32_t type) return POPCOUNT(n, 5); #endif } + +void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, + uint32_t ctrl) +{ + uint64_t ah, al, b, resh, resl; + + ah = 0; + al = d->Q((ctrl & 1) != 0); + b = s->Q((ctrl & 16) != 0); + resh = resl = 0; + + while (b) { + if (b & 1) { + resl ^= al; + resh ^= ah; + } + ah = (ah << 1) | (al >> 63); + al <<= 1; + b >>= 1; + } + + d->Q(0) = resl; + d->Q(1) = resh; +} #endif #undef SHIFT diff --git a/target-i386/ops_sse_header.h b/target-i386/ops_sse_header.h index 401eac6..2842233 100644 --- a/target-i386/ops_sse_header.h +++ b/target-i386/ops_sse_header.h @@ -336,6 +336,11 @@ DEF_HELPER_3(crc32, tl, i32, tl, i32) DEF_HELPER_3(popcnt, tl, env, tl, i32) #endif +/* AES-NI op helpers */ +#if SHIFT == 1 +DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32) +#endif + #undef SHIFT #undef Reg #undef SUFFIX diff --git a/target-i386/translate.c b/target-i386/translate.c index 7596a90..d649e99 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -3147,6 +3147,8 @@ struct SSEOpHelper_eppi { #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } +#define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \ + CPUID_EXT_PCLMULQDQ } static const struct SSEOpHelper_epp sse_op_table6[256] = { [0x00] = SSSE3_OP(pshufb), @@ -3216,6 +3218,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { [0x40] = SSE41_OP(dpps), [0x41] = SSE41_OP(dppd), [0x42] = SSE41_OP(mpsadbw), + [0x44] = PCLMULQDQ_OP(pclmulqdq), [0x60] = SSE42_OP(pcmpestrm), [0x61] = SSE42_OP(pcmpestri), [0x62] = SSE42_OP(pcmpistrm), |