aboutsummaryrefslogtreecommitdiff
path: root/target-i386
diff options
context:
space:
mode:
authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2008-06-04 17:39:33 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2008-06-04 17:39:33 +0000
commit33c263df7f87ca0cd170a6017a668205488ab010 (patch)
tree27b748ccdc0758a9af86122d1e054357ace0b2fa /target-i386
parent4f57689a8d5db61fb42434ed70142b2b0751da68 (diff)
downloadqemu-33c263df7f87ca0cd170a6017a668205488ab010.zip
qemu-33c263df7f87ca0cd170a6017a668205488ab010.tar.gz
qemu-33c263df7f87ca0cd170a6017a668205488ab010.tar.bz2
SVM: added tsc_offset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4668 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/cpu.h7
-rw-r--r--target-i386/op_helper.c5
2 files changed, 8 insertions, 4 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 9f60738..18cb6ad 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -119,9 +119,9 @@
#define ID_MASK 0x00200000
/* hidden flags - used internally by qemu to represent additional cpu
- states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
- using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
- with eflags. */
+ states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
+ redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
+ position to ease oring with eflags. */
/* current cpl */
#define HF_CPL_SHIFT 0
/* true if soft mmu is being used */
@@ -543,6 +543,7 @@ typedef struct CPUX86State {
target_phys_addr_t vm_hsave;
target_phys_addr_t vm_vmcb;
+ uint64_t tsc_offset;
uint64_t intercept;
uint16_t intercept_cr_read;
uint16_t intercept_cr_write;
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 810c466..ebeeebd 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -3005,7 +3005,7 @@ void helper_rdtsc(void)
}
helper_svm_check_intercept_param(SVM_EXIT_RDTSC, 0);
- val = cpu_get_tsc(env);
+ val = cpu_get_tsc(env) + env->tsc_offset;
EAX = (uint32_t)(val);
EDX = (uint32_t)(val >> 32);
}
@@ -4851,6 +4851,8 @@ void helper_vmrun(int aflag, int next_eip_addend)
/* enable intercepts */
env->hflags |= HF_SVMI_MASK;
+ env->tsc_offset = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.tsc_offset));
+
env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base));
env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit));
@@ -5226,6 +5228,7 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
env->intercept = 0;
env->intercept_exceptions = 0;
env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ env->tsc_offset = 0;
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base));
env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit));