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authorAndre Przywara <andre.przywara@amd.com>2009-08-19 15:42:42 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2009-08-27 19:33:15 -0500
commit400281af34e5ee6aa9f5496b53d8f82c6fef9319 (patch)
tree44de8772409c8f19479ed5499585f5b6f2301b90 /target-i386
parentac72472b5fb8411fbeb6789187d67ad7aef69133 (diff)
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set CPUID bits to present cores and threads topology
Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/helper.c28
1 files changed, 25 insertions, 3 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index afdd3e4..4d71d42 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1627,6 +1627,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
*ecx = env->cpuid_ext_features;
*edx = env->cpuid_features;
+ if (env->nr_cores * env->nr_threads > 1) {
+ *ebx |= (env->nr_cores * env->nr_threads) << 16;
+ *edx |= 1 << 28; /* HTT bit */
+ }
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
@@ -1637,21 +1641,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 4:
/* cache info: needed for Core compatibility */
+ if (env->nr_cores > 1) {
+ *eax = (env->nr_cores - 1) << 26;
+ } else {
+ *eax = 0;
+ }
switch (count) {
case 0: /* L1 dcache info */
- *eax = 0x0000121;
+ *eax |= 0x0000121;
*ebx = 0x1c0003f;
*ecx = 0x000003f;
*edx = 0x0000001;
break;
case 1: /* L1 icache info */
- *eax = 0x0000122;
+ *eax |= 0x0000122;
*ebx = 0x1c0003f;
*ecx = 0x000003f;
*edx = 0x0000001;
break;
case 2: /* L2 cache info */
- *eax = 0x0000143;
+ *eax |= 0x0000143;
+ if (env->nr_threads > 1) {
+ *eax |= (env->nr_threads - 1) << 14;
+ }
*ebx = 0x3c0003f;
*ecx = 0x0000fff;
*edx = 0x0000001;
@@ -1704,6 +1716,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx = env->cpuid_ext3_features;
*edx = env->cpuid_ext2_features;
+ if (env->nr_cores * env->nr_threads > 1 &&
+ env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
+ env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
+ env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
+ *ecx |= 1 << 1; /* CmpLegacy bit */
+ }
+
if (kvm_enabled()) {
/* Nested SVM not yet supported in KVM */
*ecx &= ~CPUID_EXT3_SVM;
@@ -1750,6 +1769,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ebx = 0;
*ecx = 0;
*edx = 0;
+ if (env->nr_cores * env->nr_threads > 1) {
+ *ecx |= (env->nr_cores * env->nr_threads) - 1;
+ }
break;
case 0x8000000A:
*eax = 0x00000001; /* SVM Revision */