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| author | Andre Przywara <andre.przywara@amd.com> | 2009-09-19 00:30:47 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-04 14:04:40 +0200 |
| commit | ccd59d09a9d0c75b86185b89d8246e40b5f01168 (patch) | |
| tree | 09abef1a743a89c5acdc88b89889ac39b4611aeb /target-i386 | |
| parent | 5f0ce17ffc926f0d41cdbf90435ff7cb33a04942 (diff) | |
| download | qemu-ccd59d09a9d0c75b86185b89d8246e40b5f01168.zip qemu-ccd59d09a9d0c75b86185b89d8246e40b5f01168.tar.gz qemu-ccd59d09a9d0c75b86185b89d8246e40b5f01168.tar.bz2 | |
target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.
If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.
This behavior is guarded by the CR8_LEGACY CPUID bit
(Fn8000_0001:ECX[1]).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 5b11d7f..0f62a97 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7351,6 +7351,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_QUAD; else ot = OT_LONG; + if ((prefixes & PREFIX_LOCK) && (reg == 0) && + (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { + reg = 8; + } switch(reg) { case 0: case 2: |