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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-18 19:19:57 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-18 19:19:57 +0000
commitcd31fefaf217330ffd31a28ab121df18ac1de5d8 (patch)
tree4b192265092d6425b55f1a2b81fdd11fbcbab5f9 /target-i386/translate.c
parentd238db7f0b18fdd4ffd13f94c16e36932574ac24 (diff)
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fixed INC/DEC condition codes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4493 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r--target-i386/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index dc7bb03..44e287b 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1312,8 +1312,8 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
gen_op_mov_reg_T0(ot, d);
else
gen_op_st_T0_A0(ot + s1->mem_index);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
gen_compute_eflags_c(cpu_cc_src);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static void gen_extu(int ot, TCGv reg)