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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-25 18:16:18 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-09-25 18:16:18 +0000
commit2436b61a6b386d712a1813b036921443bd1c5c39 (patch)
tree9a4250e083f45b100f741e007f8f02301cbdbcdc /target-i386/translate.c
parente737b32a3688d415c3b1f9d0a3fb2b941b1e758c (diff)
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SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/translate.c')
-rw-r--r--target-i386/translate.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c739d69..cd9cae2 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -6505,7 +6505,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
tcg_gen_helper_0_0(helper_rdpmc);
break;
case 0x134: /* sysenter */
- if (CODE64(s))
+ /* For Intel SYSENTER is valid on 64-bit */
+ if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
goto illegal_op;
if (!s->pe) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
@@ -6520,7 +6521,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
}
break;
case 0x135: /* sysexit */
- if (CODE64(s))
+ /* For Intel SYSEXIT is valid on 64-bit */
+ if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
goto illegal_op;
if (!s->pe) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
@@ -6530,7 +6532,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
s->cc_op = CC_OP_DYNAMIC;
}
gen_jmp_im(pc_start - s->cs_base);
- tcg_gen_helper_0_0(helper_sysexit);
+ tcg_gen_helper_0_1(helper_sysexit, tcg_const_i32(dflag));
gen_eob(s);
}
break;