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| author | Marcelo Tosatti <mtosatti@redhat.com> | 2014-04-30 13:48:45 -0300 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2014-06-25 23:54:57 +0200 |
| commit | 303752a9068bfe84b9b05f1cd5ad5ff65b7f3ea6 (patch) | |
| tree | 52d8eb601fac0ce8ac1ab6ad644b6290a64c722a /target-i386/cpu.c | |
| parent | 68bfd0ad4a1dcc4c328d5db85dc746b49c1ec07e (diff) | |
| download | qemu-303752a9068bfe84b9b05f1cd5ad5ff65b7f3ea6.zip qemu-303752a9068bfe84b9b05f1cd5ad5ff65b7f3ea6.tar.gz qemu-303752a9068bfe84b9b05f1cd5ad5ff65b7f3ea6.tar.bz2 | |
target-i386: Support "invariant tsc" flag
Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation:
17.13.1 Invariant TSC The time stamp counter in newer processors may
support an enhancement, referred to as invariant TSC. Processor’s
support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-.
and T-states. This is the architectural behavior moving forward. On
processors with invariant TSC support, the OS may use the TSC for wall
clock timer services (instead of ACPI or HPET timers). TSC reads are
much more efficient and do not incur the overhead associated with a ring
transition or access to a platform resource.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
[ehabkost: redo feature filtering to use .tcg_features]
[ehabkost: add CPUID_APM_INVTSC macro, add it to .unmigratable_flags]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-i386/cpu.c')
| -rw-r--r-- | target-i386/cpu.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b651a94..4cfb9a3 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -263,6 +263,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; +static const char *cpuid_apm_edx_feature_name[] = { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "invtsc", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -317,6 +328,7 @@ static const char *cpuid_7_0_ebx_feature_name[] = { CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ +#define TCG_APM_FEATURES 0 typedef struct FeatureWordInfo { @@ -372,6 +384,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EBX, .tcg_features = TCG_7_0_EBX_FEATURES, }, + [FEAT_8000_0007_EDX] = { + .feat_names = cpuid_apm_edx_feature_name, + .cpuid_eax = 0x80000007, + .cpuid_reg = R_EDX, + .tcg_features = TCG_APM_FEATURES, + .unmigratable_flags = CPUID_APM_INVTSC, + }, }; typedef struct X86RegisterInfo32 { @@ -2385,6 +2404,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \ (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE); break; + case 0x80000007: + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = env->features[FEAT_8000_0007_EDX]; + break; case 0x80000008: /* virtual & phys address size in low 2 bytes. */ /* XXX: This value must match the one used in the MMU code. */ |