aboutsummaryrefslogtreecommitdiff
path: root/target-cris
diff options
context:
space:
mode:
authorPeter Crosthwaite <crosthwaitepeter@gmail.com>2015-06-23 20:57:38 -0700
committerAndreas Färber <afaerber@suse.de>2015-07-09 15:20:41 +0200
commit6b625fde5eb8d1c969969392f1c92b58beed2183 (patch)
treee6b28d02044e1b58493c95de154142feca5a4b7e /target-cris
parent51d373cf5f5a39fa315342d12ec910fe59d87090 (diff)
downloadqemu-6b625fde5eb8d1c969969392f1c92b58beed2183.zip
qemu-6b625fde5eb8d1c969969392f1c92b58beed2183.tar.gz
qemu-6b625fde5eb8d1c969969392f1c92b58beed2183.tar.bz2
disas: cris: QOMify target specific disas setup
Move the target_disas() cris specifics to the QOM disas_set_info() hook and delete the cris specific code in disas.c. This also now adds support for monitor_disas() to cris. E.g. (qemu) xp 0x40004000 0000000040004000: 0x1e6f25f0 And before this patch: (qemu) xp/i 0x40004000 0x40004000: Asm output not supported on this arch After: (qemu) xp/i 0x40004000 0x40004000: di (qemu) xp/i 0x40004002 0x40004002: move.d 0xb003c004,$r1 Note: second example is 6-byte misaligned instruction! Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-cris')
-rw-r--r--target-cris/cpu.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 0db209b..b17e849 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -161,6 +161,20 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level)
}
#endif
+static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ CRISCPU *cc = CRIS_CPU(cpu);
+ CPUCRISState *env = &cc->env;
+
+ if (env->pregs[PR_VR] != 32) {
+ info->mach = bfd_mach_cris_v0_v10;
+ info->print_insn = print_insn_crisv10;
+ } else {
+ info->mach = bfd_mach_cris_v32;
+ info->print_insn = print_insn_crisv32;
+ }
+}
+
static void cris_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
@@ -292,6 +306,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 49;
cc->gdb_stop_before_watchpoint = true;
+
+ cc->disas_set_info = cris_disas_set_info;
}
static const TypeInfo cris_cpu_type_info = {