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authorRichard Henderson <rth@twiddle.net>2015-08-29 12:59:29 -0700
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:36:27 +1100
commit667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 (patch)
tree0d1aa7775d9cb83ce858394f2e56114ccdc23f94 /target-cris/translate_v10.c
parent765b842adec4c5a359e69ca08785553599f71496 (diff)
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target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-cris/translate_v10.c')
-rw-r--r--target-cris/translate_v10.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 12d7dfc..3ab1c39 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1199,9 +1199,6 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
{
unsigned int insn_len = 2;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_insn_start(dc->pc);
-
/* Load a halfword onto the instruction register. */
dc->ir = cpu_lduw_code(env, dc->pc);