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authoredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-13 10:59:14 +0000
committeredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-13 10:59:14 +0000
commitcf1d97f07480b6197aebc489938b4e1fed78d3e7 (patch)
treed4ae1d25078f714690f5b01761f2bffd5d57f115 /target-cris/mmu.h
parent3bd8c5e4f1fdb61a3eb8a4a8b6e5b4cf1156ba76 (diff)
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CRIS: Improve TLB management and handle delayslots at page boundaries.
* Dont flush the entire qemu tlb when the $pid changes. Instead we go through the guests TLB and choose entries that need to be flushed. * Add env->dslot and handle delayslots at pageboundaries. * Remove some unused code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/mmu.h')
-rw-r--r--target-cris/mmu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-cris/mmu.h b/target-cris/mmu.h
index 1d6d33f..5a1f92d 100644
--- a/target-cris/mmu.h
+++ b/target-cris/mmu.h
@@ -11,7 +11,7 @@ struct cris_mmu_result_t
int bf_vec;
};
-target_ulong cris_mmu_tlb_latest_update(CPUState *env);
+void cris_mmu_flush_pid(CPUState *env, uint32_t pid);
int cris_mmu_translate(struct cris_mmu_result_t *res,
CPUState *env, uint32_t vaddr,
int rw, int mmu_idx);