diff options
author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
---|---|---|
committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
commit | 6ebbf390003270afece028facef4d9834df81a8c (patch) | |
tree | adc8e9a3d586d5b1b550543fceb6ffdaeda03f6a /target-cris/helper.c | |
parent | d0f48074dbc21248f3b0a9fb48126cb0d95991b5 (diff) | |
download | qemu-6ebbf390003270afece028facef4d9834df81a8c.zip qemu-6ebbf390003270afece028facef4d9834df81a8c.tar.gz qemu-6ebbf390003270afece028facef4d9834df81a8c.tar.bz2 |
Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/helper.c')
-rw-r--r-- | target-cris/helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c index 3db3bea..9830560 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -35,7 +35,7 @@ void do_interrupt (CPUState *env) } int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, - int is_user, int is_softmmu) + int mmu_idx, int is_softmmu) { env->exception_index = 0xaa; env->debug1 = address; @@ -52,7 +52,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) #else /* !CONFIG_USER_ONLY */ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu) + int mmu_idx, int is_softmmu) { struct cris_mmu_result_t res; int prot, miss; @@ -61,7 +61,7 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; // printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu); - miss = cris_mmu_translate(&res, env, address, rw, is_user); + miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); if (miss) { /* handle the miss. */ @@ -73,7 +73,7 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, phy = res.phy; } // printf ("a=%x phy=%x\n", address, phy); - return tlb_set_page(env, address, phy, prot, is_user, is_softmmu); + return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); } |