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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 15:59:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 16:01:03 +0100 |
| commit | fe8fcf3d642b4de1369841bf6acac13e0ec8770d (patch) | |
| tree | 2c41b2e3abf67957ea1b75e7d5330ab2b1dff4fe /target-arm | |
| parent | b93dbcdd5993dd0800d18d494f60821a398fee8b (diff) | |
| download | qemu-fe8fcf3d642b4de1369841bf6acac13e0ec8770d.zip qemu-fe8fcf3d642b4de1369841bf6acac13e0ec8770d.tar.gz qemu-fe8fcf3d642b4de1369841bf6acac13e0ec8770d.tar.bz2 | |
target-arm: Don't permit ARMv8-only Neon insns on ARMv7
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
so they need a guard to make them UNDEF if the CPU only supports ARMv7.
(We got this right for all the other new-in-v8 insns, but forgot
it for these Neon 2-reg-misc ops.)
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1465492511-9333-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 6815bc1a..3e71467 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5311,6 +5311,30 @@ static int neon_2rm_is_float_op(int op) op >= NEON_2RM_VRECPE_F); } +static bool neon_2rm_is_v8_op(int op) +{ + /* Return true if this neon 2reg-misc op is ARMv8 and up */ + switch (op) { + case NEON_2RM_VRINTN: + case NEON_2RM_VRINTA: + case NEON_2RM_VRINTM: + case NEON_2RM_VRINTP: + case NEON_2RM_VRINTZ: + case NEON_2RM_VRINTX: + case NEON_2RM_VCVTAU: + case NEON_2RM_VCVTAS: + case NEON_2RM_VCVTNU: + case NEON_2RM_VCVTNS: + case NEON_2RM_VCVTPU: + case NEON_2RM_VCVTPS: + case NEON_2RM_VCVTMU: + case NEON_2RM_VCVTMS: + return true; + default: + return false; + } +} + /* Each entry in this array has bit n set if the insn allows * size value n (otherwise it will UNDEF). Since unallocated * op values will have no bits set they always UNDEF. @@ -6798,6 +6822,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if ((neon_2rm_sizes[op] & (1 << size)) == 0) { return 1; } + if (neon_2rm_is_v8_op(op) && + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return 1; + } if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) && q && ((rm | rd) & 1)) { return 1; |