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| author | Andreas Färber <afaerber@suse.de> | 2013-06-21 20:20:45 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-23 02:41:32 +0200 |
| commit | ed2803da58355413447f8c7c681a76873168114f (patch) | |
| tree | 3772ea93bce05d67ccbd4194eb77173dc46a5706 /target-arm | |
| parent | 801c4c287b7d85fe8447900f78a9a6ab89d00271 (diff) | |
| download | qemu-ed2803da58355413447f8c7c681a76873168114f.zip qemu-ed2803da58355413447f8c7c681a76873168114f.tar.gz qemu-ed2803da58355413447f8c7c681a76873168114f.tar.bz2 | |
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 7b50c8c..6db4c50 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9911,6 +9911,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, TranslationBlock *tb, bool search_pc) { + CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; DisasContext dc1, *dc = &dc1; CPUBreakpoint *bp; @@ -9930,7 +9931,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; - dc->singlestep_enabled = env->singlestep_enabled; + dc->singlestep_enabled = cs->singlestep_enabled; dc->condjmp = 0; dc->thumb = ARM_TBFLAG_THUMB(tb->flags); dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags); @@ -10080,7 +10081,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * ensures prefetch aborts occur at the right place. */ num_insns ++; } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && - !env->singlestep_enabled && + !cs->singlestep_enabled && !singlestep && dc->pc < next_page_start && num_insns < max_insns); @@ -10097,7 +10098,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (unlikely(env->singlestep_enabled)) { + if (unlikely(cs->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { gen_set_condexec(dc); |