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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-05-05 18:36:10 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2004-05-05 18:36:10 +0000
commitbeddab753d0b3e971bfe46f165524a1c24229c29 (patch)
treee8b943424e1f792ba2d5641fc3aa0920f9ccc4f4 /target-arm
parent512176dbd81b0afb7185416ab2a28a340978b85b (diff)
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arm load/store half word fix (Ulrich Hecht)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@785 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/translate.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f405a23..00bdbb9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -543,7 +543,8 @@ static void disas_arm_insn(DisasContext *s)
rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf;
gen_movl_T1_reg(s, rn);
- gen_add_datah_offset(s, insn);
+ if (insn & (1 << 24))
+ gen_add_datah_offset(s, insn);
if (insn & (1 << 20)) {
/* load */
switch(sh) {