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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2015-06-15 18:06:10 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-15 18:06:10 +0100 |
| commit | a8e81b319d1ae1224cc7059877dcdf04a5aad59d (patch) | |
| tree | 82ea3a2bd89c848a1135e183a157bf12a9968e4e /target-arm | |
| parent | b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 (diff) | |
| download | qemu-a8e81b319d1ae1224cc7059877dcdf04a5aad59d.zip qemu-a8e81b319d1ae1224cc7059877dcdf04a5aad59d.tar.gz qemu-a8e81b319d1ae1224cc7059877dcdf04a5aad59d.tar.bz2 | |
arm: Implement uniprocessor with MP config
Add a boolean for indicating uniprocessors with MP extensions. This
drives the U bit in MPIDR. Prepares support for Cortex-R5.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu-qom.h | 3 | ||||
| -rw-r--r-- | target-arm/helper.c | 6 |
2 files changed, 7 insertions, 2 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 24a4cfb..57b4a12 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -116,6 +116,9 @@ typedef struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* Uniprocessor system with MP extensions */ + bool mp_is_up; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target-arm/helper.c b/target-arm/helper.c index f51dece..f038a03 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2075,9 +2075,11 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set - * bit 30. (For instance, A9UP.) However we do - * not currently model any of those cores. + * bit 30. (For instance, Cortex-R5). */ + if (cpu->mp_is_up) { + mpidr |= (1u << 30); + } } return mpidr; } |