diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 15:59:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-14 15:59:12 +0100 |
| commit | 811595a2d4ab8c6354857a50ffd29fafce52a892 (patch) | |
| tree | a351ae57ff1c04d5b136c9f3deef1727ad4c9b05 /target-arm | |
| parent | 8433dee02777e81144a520143fa937672a6936e0 (diff) | |
| download | qemu-811595a2d4ab8c6354857a50ffd29fafce52a892.zip qemu-811595a2d4ab8c6354857a50ffd29fafce52a892.tar.gz qemu-811595a2d4ab8c6354857a50ffd29fafce52a892.tar.bz2 | |
target-arm: Fix reset and migration of TTBCR(S)
Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32
TTBCR(S) register if the guest used non-LPAE page tables. This is
because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS,
meaning that the AArch64 variant has to handle migration and reset.
Although AArch64 TCR_EL3 doesn't need to care about the mask and
base_mask fields, AArch32 may do so, and so we must use the special
TTBCR reset and raw write functions to ensure they are set correctly.
This doesn't affect TCR_EL2, because the AArch32 equivalent of that
is HTCR, which never uses the non-LPAE page table variant.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Pranith Kumar <bobby.prani+qemu@gmail.com>
Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org>
Message-id: 1465488181-31977-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 862e780..c9730d6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3765,8 +3765,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, .access = PL3_RW, /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. */ + .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, |