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| author | Alexander Graf <agraf@suse.de> | 2013-12-17 19:42:35 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 20:12:51 +0000 |
| commit | 82e14b02a2bd822af6db2ef728a1698b9a24e50c (patch) | |
| tree | 186114efe0c06ac74cd284f42d6393df547e8150 /target-arm | |
| parent | 680ead216e666e5cc192fe86adf30563999a5dd8 (diff) | |
| download | qemu-82e14b02a2bd822af6db2ef728a1698b9a24e50c.zip qemu-82e14b02a2bd822af6db2ef728a1698b9a24e50c.tar.gz qemu-82e14b02a2bd822af6db2ef728a1698b9a24e50c.tar.bz2 | |
target-arm: A64: add support for 1-src RBIT insn
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper-a64.c | 18 | ||||
| -rw-r--r-- | target-arm/helper-a64.h | 1 | ||||
| -rw-r--r-- | target-arm/translate-a64.c | 20 |
3 files changed, 39 insertions, 0 deletions
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index e4c5346..cccaac6 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -49,3 +49,21 @@ uint64_t HELPER(clz64)(uint64_t x) { return clz64(x); } + +uint64_t HELPER(rbit64)(uint64_t x) +{ + /* assign the correct byte position */ + x = bswap64(x); + + /* assign the correct nibble position */ + x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4) + | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4); + + /* assign the correct bit position */ + x = ((x & 0x8888888888888888ULL) >> 3) + | ((x & 0x4444444444444444ULL) >> 1) + | ((x & 0x2222222222222222ULL) << 1) + | ((x & 0x1111111111111111ULL) << 3); + + return x; +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index b10b6c3..9959139 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -19,3 +19,4 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e5481da..0ed21fc 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1062,6 +1062,24 @@ static void handle_clz(DisasContext *s, unsigned int sf, } } +static void handle_rbit(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + gen_helper_rbit64(tcg_rd, tcg_rn); + } else { + TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); + gen_helper_rbit(tcg_tmp32, tcg_tmp32); + tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); + tcg_temp_free_i32(tcg_tmp32); + } +} + /* C3.5.7 Data-processing (1 source) * 31 30 29 28 21 20 16 15 10 9 5 4 0 * +----+---+---+-----------------+---------+--------+------+------+ @@ -1084,6 +1102,8 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) switch (opcode) { case 0: /* RBIT */ + handle_rbit(s, sf, rn, rd); + break; case 1: /* REV16 */ case 2: /* REV32 */ case 3: /* REV64 */ |