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| author | Rabin Vincent <rabin@rab.in> | 2010-02-15 00:02:36 +0530 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2010-02-19 15:20:21 +0000 |
| commit | 30a8cac1399306963cb3dd65e0421f957d8b4da7 (patch) | |
| tree | 8edc2035c978ada696cb5f877e25991bd659a4ff /target-arm | |
| parent | b8b45b68f8836c1db8422badf3c0c573a88f8b43 (diff) | |
| download | qemu-30a8cac1399306963cb3dd65e0421f957d8b4da7.zip qemu-30a8cac1399306963cb3dd65e0421f957d8b4da7.tar.gz qemu-30a8cac1399306963cb3dd65e0421f957d8b4da7.tar.bz2 | |
target-arm: support thumb exception handlers
When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 27001e8..6f40084 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -824,11 +824,10 @@ void do_interrupt(CPUARMState *env) env->spsr = cpsr_read(env); /* Clear IT bits. */ env->condexec_bits = 0; - /* Switch to the new mode, and switch to Arm mode. */ - /* ??? Thumb interrupt handlers not implemented. */ + /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; env->uncached_cpsr |= mask; - env->thumb = 0; + env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; env->regs[14] = env->regs[15] + offset; env->regs[15] = addr; env->interrupt_request |= CPU_INTERRUPT_EXITTB; |