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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-08-19 18:56:27 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-19 19:02:40 +0100 |
| commit | f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0 (patch) | |
| tree | 1ecd99b80f64f144a285fa3380d5642677245608 /target-arm | |
| parent | 863714ba6cdc09d1a84069815dc67c8da66b0a29 (diff) | |
| download | qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.zip qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.tar.gz qemu-f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0.tar.bz2 | |
arm: cortex-a9: Fix cache-line size and associativity
For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.
QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e27cca2..8199f32 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -715,8 +715,8 @@ static void cortex_a9_initfn(Object *obj) cpu->id_isar4 = 0x00111142; cpu->dbgdidr = 0x35141000; cpu->clidr = (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ + cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } |