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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2015-09-08 17:38:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-09-08 17:38:44 +0100
commitc96fc9b52d0a318d8026a0bcaba204d319ad91e0 (patch)
tree2c5a741aea689752af57404dcfffb3e080460e8b /target-arm
parent7a379c7e68f1b2286602b0beeeb58dcef7c9e760 (diff)
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target-arm: Add AArch64 access to PAR_EL1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/helper.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 38a05e1..fc4b65f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2993,6 +2993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+ { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
+ .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
+ .writefn = par_write },
#endif
/* TLB invalidate last level of translation table walk */
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,