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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-04-07 20:30:53 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-04-07 20:30:53 +0000
commit6d9a42be17f1961f05dd247d5277747b9cea631e (patch)
tree6069021c9e433dae9e50121ba3d2557ff63a3baf /target-arm
parent26fb5e48d9b4ab676b7b78e0f38e8e4ed126f047 (diff)
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Implement ARM floating point exception emulation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4166 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/nwfpe/fpa11.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target-arm/nwfpe/fpa11.c b/target-arm/nwfpe/fpa11.c
index 6b43500..626a87a 100644
--- a/target-arm/nwfpe/fpa11.c
+++ b/target-arm/nwfpe/fpa11.c
@@ -162,6 +162,8 @@ unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs)
fpa11->initflag = 1;
}
+ set_float_exception_flags(0, &fpa11->fp_status);
+
if (TEST_OPCODE(opcode,MASK_CPRT))
{
//fprintf(stderr,"emulating CPRT\n");
@@ -191,6 +193,11 @@ unsigned int EmulateAll(unsigned int opcode, FPA11* qfpa, CPUARMState* qregs)
}
// restore_flags(flags);
+ if(nRc == 1 && get_float_exception_flags(&fpa11->fp_status))
+ {
+ //printf("fef 0x%x\n",float_exception_flags);
+ nRc=-get_float_exception_flags(&fpa11->fp_status);
+ }
//printf("returning %d\n",nRc);
return(nRc);