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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-04-20 07:39:15 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-04-27 11:06:18 +0000 |
| commit | c5fad12fa08228d0c2f04089ba0cd27718f1b723 (patch) | |
| tree | 11ae7d19c76bda0b22e0aed311546c5a0cd576e3 /target-arm | |
| parent | 778c3a0619f3b47f94e566ca4f656aabe5f4b3d6 (diff) | |
| download | qemu-c5fad12fa08228d0c2f04089ba0cd27718f1b723.zip qemu-c5fad12fa08228d0c2f04089ba0cd27718f1b723.tar.gz qemu-c5fad12fa08228d0c2f04089ba0cd27718f1b723.tar.bz2 | |
target-arm: Move A9 config_base_address reset value to ARMCPU
Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.
Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-arm/cpu.c | 4 |
2 files changed, 2 insertions, 3 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 2891521..a61c68d 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -93,6 +93,7 @@ typedef struct ARMCPU { * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ uint32_t ccsidr[16]; + uint32_t reset_cbar; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 2e0eccd..7eb323a 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s) ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - uint32_t tmp = 0; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - tmp = env->cp15.c15_config_base_address; memset(env, 0, offsetof(CPUARMState, breakpoints)); - env->cp15.c15_config_base_address = tmp; + env->cp15.c15_config_base_address = cpu->reset_cbar; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |