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| author | Jan Kiszka <jan.kiszka@web.de> | 2011-04-09 13:18:59 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-04-27 20:04:51 +0200 |
| commit | 47f7be394aa7baf7855fe78f56b8ba4c69bf75d9 (patch) | |
| tree | 9633e60e984359013a156d84e3f6c3c9ac6a0cea /target-arm | |
| parent | 661bfc80e876d32da8befe53ba0234d87fc0bcc2 (diff) | |
| download | qemu-47f7be394aa7baf7855fe78f56b8ba4c69bf75d9.zip qemu-47f7be394aa7baf7855fe78f56b8ba4c69bf75d9.tar.gz qemu-47f7be394aa7baf7855fe78f56b8ba4c69bf75d9.tar.bz2 | |
ioapic: Do not set irr for masked edge IRQs
So far we set IRR for edge IRQs even if the pin is masked. If the guest
later on unmasks and switches the pin to level-triggered mode, irr will
remain set, causing an IRQ storm. The point is that setting IRR is not
correct in this case according to the spec, and avoiding this resolves
the issue.
Reported-and-tested-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
0 files changed, 0 insertions, 0 deletions