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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-05-27 17:09:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-05-27 17:09:49 +0100 |
| commit | f0aff25570003fc618c47dec36852fc7d80436ee (patch) | |
| tree | 8cae884e9624845875a42845a479f9ab2d46adff /target-arm/translate.h | |
| parent | fc37b7a0b0cebe4118d172c4fceb0acc2fa25b4a (diff) | |
| download | qemu-f0aff25570003fc618c47dec36852fc7d80436ee.zip qemu-f0aff25570003fc618c47dec36852fc7d80436ee.tar.gz qemu-f0aff25570003fc618c47dec36852fc7d80436ee.tar.bz2 | |
target-arm: implement CPACR register logic for ARMv7
In ARMv7 the CPACR register allows to control access rights to
coprocessor 0-13 interfaces. Bits corresponding to unimplemented
coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
Treating TRCDIS as RAZ/WI since we neither implement a trace
macrocell nor a CP14 interface to the trace macrocell registers.
Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
bit in the TB flags, flushing the TLB is not necessary anymore.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1400532968-30668-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.h')
0 files changed, 0 insertions, 0 deletions